I. INTRODUCTION
DC power supply is an essential electric power source of various electronic products. Using a full-bridge diode rectifier with a large filter capacitor as the front-end rectification to obtain DC output voltage is the conventional method. However, this method will encounter excessively large peak input current and high harmonic distortion. Its input power factor is lower by approximately 0.5–0.6, which does not meet the IEC61000-3-2 limits. Thus, electronic product designers must conduct research on how to reduce input current harmonics and enhance input power factor for their DC power supplies. Inserting a power factor correction (PFC) circuit into the DC power supply is the most common method.
In various active power factor correctors, the boost power factor corrector is the most general circuit, as shown in Fig. 1(a) [1]-[7]. However, its conduction losses are large because its power current flow paths always include three main power semiconductors. Moreover, the commutation losses of its main power semiconductors are also large because its main power semiconductors are operated under hard-switching conditions.
Fig. 1.(a) Conventional PFC boost rectifier [1], (b) basic two-switch bridgeless PFC boost rectifier [11], (c) totem pole bridgeless PFC boost rectifier [14], and (d) proposed high-performance rectifier.
Several power factor correctors with low conduction losses are proposed to address this problem [11]-[14]. These power factor correctors are the basic two-switch bridgeless PFC boost rectifier, as shown in Fig. 1(b) [11]-[13], and the totem pole bridgeless PFC boost rectifier, as shown Fig. 1(c) [14]. Their conduction losses are certainly lower than previous topologies because their power current flow paths only include two main power semiconductors. Several soft-switching topologies have been proposed to improve their commutation losses [15]-[19]. In previous topologies, the voltage stresses of their main active power switches are equal to the output voltage Vo. However, reducing voltage stress of semiconductors is a more important matter because the cost of semiconductors is dependent on the rated operation voltage.
A high-performance rectifier is proposed in this study, as shown in Fig. 1(d), to reduce conduction losses and commutation losses. The conduction losses in the proposed rectifier are certainly lower than those in previous topologies because the power current flow path when the main switches are turned on only includes two main power semiconductors and the power current flow path when the main switches are turned off only includes one main power semiconductor. Moreover, the proposed rectifier uses a ZCS auxiliary circuit to derive the ZCS function for its power semiconductors to improve commutation losses. The efficiency of the proposed rectifier will be higher than that in previously mentioned topologies. Moreover, the voltage stress of its main active power switches is equal to Vo/2 and is lower than one of the previously mentioned topologies. Thus, the main circuit cost of the proposed rectifier can be decreased. The comparisons of the number of semiconductors in the power current flow path and the voltage stress on the main semiconductors are shown in Tables I and II, respectively.
Table ICOMPARISON OF VOLTAGE STRESS ON THE MAIN SWITCHES AND DIODES IN DIFFERENT RECTIFIERS
Table IICOMPARISON OF THE NUMBER OF SEMICONDUCTORS IN THE CURRENT FLOW PATH
Accordingly, low voltage stresses, low switching losses, low conduction losses, and low EMI noise can be achieved in the proposed rectifier. In the control strategy, its controller uses the average current mode control to achieve fixed-frequency current control with stability and low distortion. Thus, the proposed rectifier has good dynamic characteristics. Its behavior is described by seven transition states during one switching period in the positive half-line period. A design strategy is built and a physical system of the 1 kW proposed rectifier is generated to assess system performance.
II. PRINCIPLE OF THE PROPOSED HIGH-PERFORMANCE RECTIFIER
A. Circuit Description
A power stage diagram of the proposed rectifier is shown in Fig. 1(d). The proposed rectifier is composed of a bridgeless PFC boost rectifier with low conduction losses and low voltage stress and a ZCS auxiliary circuit. The bridgeless PFC boost rectifier with low conduction losses and low voltage stress is operated in continuous conduction mode (CCM). Moreover, it is composed of an input inductor Lin, two main switches Sm1 and Sm2, two main diodes D1 and D2, and two output capacitors Co1 and Co2. The bridgeless PFC boost rectifier performs certain functions, such as PFC.
The ZCS auxiliary circuit is composed of two diodes Da1 and Da2, two resonant inductors Lr1 and Lr2, two resonant capacitors Cr1 and Cr2, and two switches Sa1 and Sa1, which are rated as small power compared with the output power. The ZCS auxiliary circuit is used to perform ZCS functions for all power semiconductors in the proposed rectifier.
B. Principle of Operation
The drive signals of the main power switches (Sm1 and Sm2) in the proposed rectifier are shown in Fig. 2(b). These main power switches are the same. Thus, both main switches are simultaneously turned on and off and the control circuit can be simplified. Moreover, the commercial PFC IC can be employed and the control circuit cost can be reduced. In the positive half cycle of the input line voltage, the current flows through the switch Sm1 and the antiparallel diode of switch Sm2 when the switches Sm1 and Sm2 are turned on. The power current flow path is changed to flow through diode D1 when the switches Sm1 and Sm2 are turned off. Similarly, in the negative half cycle of the input line voltage, the current flows through the switch Sm2 and the antiparallel diode of switch Sm1 when the switches Sm1 and Sm2 are turned on. The power current flow path is changed to flow through diode D2 when the switches Sm1 and Sm2 are turned off. Thus, lower conduction losses are achieved because the power current flow path only includes two power semiconductors when the switches Sm1 and Sm2 are turned on and the power current flow path only includes one power semiconductor when the switches Sm1 and Sm2 are turned off. Moreover, the proposed rectifier uses a dual boost rectifier topology. In one boost rectifier, which is composed of Lin, Sm1, the antiparallel diode of switch Sm2, D1, and Co1 is operated in the positive half cycle of the input line voltage. In another boost rectifier, which is composed of Lin, Sm2, the antiparallel diode of switch Sm1, D2, and Co2 is operated in the negative half cycle of the input line voltage. Both rectifiers show symmetrical topology. The voltages across Co1 and Co2 of the proposed rectifier without the additional balance circuit are approximately the same. Thus, the voltages across Co1 and Co2 are approximately equal to Vo/2. Moreover, the voltage stress across the main power switches is approximately equal to Vo/2.
Fig. 2.(a) Topological states for operation mode. (b) Gate signals of main switches.
C. State of Operation of the Proposed High-performance Rectifier
In the proposed rectifier circuit, circuit operation in the positive half cycle of the input line voltage is the same as that in the negative half cycle of the input line voltage. Thus, only the circuit operation in the positive half cycle of the input line voltage is described in this study to simplify the analysis. Given that the proposed rectifier is focused on higher power demand, it is operated in CCM. The operation of the ZCS auxiliary circuit has a short time interval compared with one switching period. Thus, input current iin and output voltage vo can be assumed to be constant values Iink and Vo in the kth switching period, respectively. In addition, the following assumptions are made during one switching cycle:
Based on these assumptions, circuit operations in one switching cycle can be divided into seven states. The seven dynamic equivalent circuits and the ideal relevant waveforms of the proposed rectifier during one switching period are shown in Figs. 3 and 4, respectively.
Fig. 3.The topology states of the proposed high-performance rectifier.
Fig. 4.Waveform diagram of the proposed high-performance rectifier under the kth switching period in the positive half cycle of the input line voltage.
STATE 1: [tk0, tk1], Fig. 3(a).
Before state 1, Sm1 and Sm2 maintain a turn-off state. The energy stored in inductors Lin and Lr1 are delivered to capacitor Co1 through D1. This state starts when the gates of Sm1 and Sm2 are triggered. Sm1 is turned on under ZCS. Although Sm2 is triggered, it is not turned on. Resonant inductor Lr1 discharges linearly by output voltage Vo. Resonant current iLr(t) decreases from Iink to zero. The state is completed when iLr(t) reaches zero and diode D1 is naturally turned off.
STATE 2: [tk1, tk2], Fig. 3(b).
Inductor Lin is charged by Vink at this time. The other semiconductors maintain a turn-off state.
STATE 3: [tk2, tk3], Fig. 3(c).
When Sa1 is turned on under ZCS, the resonance behavior of Cr1 and Lr1 starts and this state also starts. The resonant path is through Vo1, Lr1, Cr1, and Sa1. iLr1(t) initially increases and then decreases when it reaches its peak value. vCr1(t) also increases. When iLr1(t) drops to zero, the state ends.
STATE 4: [tk3, tk4], Fig. 3(d).
During this state, the resonance behavior of Cr1 and Lr1 is on hold. However, the resonant path is changed through Vo1, Lr1, Cr1, Da1, Sm1, and the antiparallel diode of Sm2. Although the resonant current can flow through the antiparallel diode of Sa1, the resonant current still only flows through Sm1 and the antiparallel diode of Sm2. This phenomenon occurs because the voltage drop of Sm1 and antiparallel diode of Sm2 counterbalances the voltage drop of the antiparallel diode of Sa1, which makes the low impedance current path flow through Sm1 and the antiparallel diode of Sm2. Moreover, based on Kirchhoff’s current law, ism1=iin-iLr1. Given that iLr is less than iin and ism1 is positive, no current flows through Sm2 and the current flows through the antiparallel diode of Sm2. vCr1(t) decreases and iLr1(t) increases. This state ends when iLr1(t) increases to Iink.
STATE 5: [tk4, tk5], Fig. 3(e).
The previous resonance operation is still maintained in this state. However, the resonant path is changed again and the resonant current flows through Vo1, Lr1, Cr1, and the antiparallel diode of Sa1. Given that the resonant current iLr1 is larger than the input current iin, the antiparallel diode of Sm2 is reverse biased and is naturally turned off. Thus, no current flows through Sm1, Sm2, and Sa1. Turning Sm1, Sm2, and Sa1 off is recommended under zero-current conditions. Thus, Sm1, Sm2, and Sa1 are turned off at t = tk4. vCr1(t) continuously decreases. iLr1(t) initially increases and then decreases when it reaches its peak value. This state ends when iLr1(t) drops to Iink again.
STATE 6: [tk5, tk6], Fig. 3(f).
The resonant capacitor Cr1 is discharged through Da1, Cr1, Lr1, and Vo1 in this state. Therefore, vCr1(t) decreases linearly toward zero. This state ends when vCr1(t) drops to zero again.
STATE 7: [tk6, tk7], Fig. 3(g).
In this state, input inductor Lin is charged by Vink. This state is maintained until Sm1 is again turned on under zero-current conditions.
After state 7, the state of the circuit operation is restored to the first state. vCr1(t) equals zero and iLr1(t) also equals Iink. Thus, the previous assumption is still valid.
D. Output Characteristics
The inductor voltage must satisfy Kirchhoff’s voltage law under one switching period because the proposed rectifier is operated in the steady state. Thus,
where:
The voltage conversion ratio (M) can be expressed in Equation (7):
Moreover, the voltage conversion ratios of the other topologies shown in Fig. 1 are identical and equal to The voltage conversion ratio of the proposed rectifier without ZCS auxiliary circuit is Thus, the proposed rectifier has a voltage doubler characteristic compared with the other topologies. In addition, the voltage conversion ratio of the proposed rectifier with ZCS auxiliary circuit shown in Equation (7) reveals that fs/fr will influence the voltage conversion ratio. Given that the ZCS auxiliary circuit has an auxiliary role, a small fs/fr is recommended to reduce its effect.
E. Commutation Analysis
From the operation analysis of stage 5, the constraint of the following inequalities should be satisfied to achieve soft commutation in the proposed high-performance rectifier:
Moreover, the turn-on time interval Δton,Sa1,2 of switch Sa1,2 must be less than the minimum conduction time.
where Dmin is the minimum duty cycle.
The time interval Δton,Sa1,2 is governed by the following expression:
III. CONTROL STRATEGY
The functional block diagram of the controller of the proposed high-performance rectifier is shown in Fig. 5(a). Moreover, the details of the control circuit of the proposed high-performance rectifier are shown in Fig. 5(b). The controller can be divided into two sections, namely, main PFC part and soft-switching control logic part. The main PFC part adopts the average current mode control method to correct the power factor. This study uses the commercial PFC control IC UC3854, which is produced by Texas Instruments Company, to perform basic PFC functions. The function block diagram of the IC UC3854 is shown in Fig. 5(a). For obtaining close unity power factor, UC3854 senses the synchronous line input voltage from transformer T. Moreover, it uses a multiplier/divider to combine several necessary signals, which include the feedforward synchronous line input voltage, the root–mean–square line input voltage, and the output feedback error voltage, to generate the current reference of the current error amplifier. The current error amplifier in the UC3854 uses the current reference and the output current signal of the Hall effect sensor to generate the error current to achieve the average current mode control function. Then, the error current signal enters the pulse width modulator. The pulse width modulator uses a comparator to compare the error current with the sawtooth waveform, which is a constant frequency signal used to generate the main PFC PWM control signal; this signal is in pin 16 of the UC3854.
Fig. 5.(a) Functional block diagram of the controller of the proposed high-performance rectifier. (b) Details of the circuit of the proposed high-performance rectifier controller.
Then, the main PFC PWM control signal enters the soft-switching control logic part, which is composed of a monostable multivibrator, tow comparators, several logic gates, and four drive circuits, to obtain soft-switching control signals. Fig. 5(b) shows that the two comparators are used to determine the operational cycle of the input line voltage. First, the main PFC PWM control signal triggers the monostable multivibrator (IC CD4047) through the negative edge trigger mode. Then, the monostable multivibrator outputs a constant pulse width, which is the control signal of the auxiliary switches. The constant pulse width is distributed to auxiliary switches Sa1 and Sa2 according to the output signals of the two comparators. If the proposed rectifier operates in the positive half cycle of the input line voltage, then the constant pulse width signal is transmitted to drive Sa1; otherwise, it is transmitted to drive Sa2. Moreover, with regard to the generation method of the control signals of the main power switches (Sm1 and Sm2), the main switches must maintain the turn-on state when the auxiliary switches are turned on according to previous main power circuit analysis. The main PFC PWM control signal must be synthesized with the constant pulse width signal by the OR gate to generate the new PFC PWM control signal. Given that the main switches (Sm1 and Sm2) are simultaneously turned on and off according to the previous main power circuit analysis, the new PFC PWM control signal directly triggers the two power switches.
IV. DESIGN CONSIDERATIONS AND EXPERIMENTAL RESULTS
A high-performance rectifier is designed and employed as an example. Its specifications are listed as follows:
The implemented power stage circuit of the proposed rectifier is shown in Fig. 5(a) and is focused on higher power demand. Therefore, the implemented power stage circuit of the proposed rectifier is operated under CCM. Its design procedure is described along with the previously described circuit characteristics, as follows:
1) Consideration of the Input Current Ripple and Selection of the Input Inductor Lin: When the input line voltage is at its maximum, the duty ratio D is at its minimum and can be calculated according to the conversion ratio of the conventional boost converter, as follows:
The input ripple current is also at its maximum value at this time, which can be denoted as follows:
The input ripple current is selected as 10% input maximum current. Thus,
Therefore, Lin = 680 μH is selected.
2) Selection of the Output Capacitor: The selection of the output capacitor is dependent on the switching frequency ripple current, the second harmonic ripple current, the output ripple voltage, and the hold-up time. The hold-up time is defined as the time required for the output voltage to remain within regulation after the AC input voltage is removed. However, the hold-up time often dominates the other factors in output capacitor selection. The output capacitor Co will be selected according to the hold-up time requirements. Thus,
where Δt is the hold-up time, Po,max is the maximum output power, Vo is the output voltage, and Vo(min) is the minimum output voltage that the load can normally operate.
In this case, Δt = 34 ms, Po = 1,000 W, Vo = 400 V, and Vo(min) = 300 V. Thus, Co is 971 μF. Co = 940 μF is selected.
3) Selection of the Resonant Parameters: Based on the specifications, the maximum input current can be obtained when the output power is rated as the maximum power, as follows:
Thus, the peak input current is defined as follows:
Equation (7) shows that the voltage conversion ratio is relative to parameters D and fs/fr. The lower the value of fs/fr, the lower the effect of the ZCS switching cell. Thus, the value of fs/fr is recommended to be lower than 0.3. In this case, fs/fr = 0.1 is selected. Thus,
The inequality in (8) should be satisfied to ensure that the main power switch turns on and off under ZCS. Thus,
Thus, expression (18) divided by (17) results in the following equation:
Lr1 = Lr2 = Lr = 4 μH is selected to clear the occurrence of zero-current switching. By substituting Lr = 4 μH into (17), Cr = 39.59 nF can be obtained, and Cr1 = Cr2 = Cr = 47 nF is selected.
4) Selection of the Main Power Switches and Diodes: From the circuit operation analysis, the maximum current through the main switches (Sm1, Sm2) and the main diodes (D1, D2) and the maximum voltages across them can be calculated as follows:
5) Selection of the auxiliary power switches and diodes.
From the circuit operation analysis, the maximum current through auxiliary switch Sa and the maximum voltage across it can also be obtained as follows:
In addition, the maximum current through auxiliary diodes Da1 and Da2 and the maximum voltage across them can also be obtained as follows:
Thus, IRFP 264 and DSEP30-06A MOSFETs are selected as the power switches and diodes to fulfill the hardware requirements. UC3854 is selected as the controller. The circuit parameters of the UC3854 controller can be defined according to [20]. Fig. 6(a) illustrates the experimental platform for this work. The waveforms of the input voltage and current are almost in phase and the measured power factor is more than 0.99, as shown in Fig. 6(b). A high power factor has been achieved. The commutation phenomenon in main switches Sm1 and Sm2, auxiliary switches Sa1 and Sa2, and main diodes D1 and D2 is measured and shown in Figs. 6(c), 6(d), and 7(a), respectively. The experimental results shown in Figs. 6(c), 6(d), and 7(a) reveal that ZCS is achieved for these active switches (Sm1, Sm2, and Sa). Main diodes D1 and D2 were also softly commutated under ZCS. Therefore, the switching losses for the main switches and main diodes are practically zero. Moreover, the voltage stresses of the active power switches are equal to Vo/2 = 200 V according to the experimental results shown in Figs. 6 and 7. The voltage stresses of the active power switches in other topologies with soft-switching technique [15]-[19] are equal to half of that in the topologies [15]-[19]. Lower voltage stress on the active power switches in the proposed rectifier has been achieved and verified.
Fig. 6.(a) Experimental platform. (b) Waveforms of input voltage vin(t) and input current iin(t) under 1,000 W output power rating. vin = 50 V/div; iin = 10 A/div; time = 4 m/div. (c) Commutation in main switches Sm1 and Sm2 under 1,000 W output power rating. VDSm1, VDSm2 = 100 V/div; IDSm1, IDSm2 = 10 A/div; time = 2 μs/div. (d) Commutation in main diodes D1 and D2 under 1,000 W output power rating. VD1, VD2 = 250 V/div; ID1, ID2 = 10 A/div; time = 4 μs/div.
Fig. 7.(a) Commutation in auxiliary switches Sa1 and Sa2 under 1,000 W output power rating. VDSa1, VDSa2 = 100 V/div; IDSa1, IDSa2 = 10 A/div; time = 4 μs/div.(b) Power factor according to the output power. (c) Experimental efficiency of the proposed ZCS bridgeless PFC boost rectifier compared with the other topologies. (d) Transient waveforms of the output voltage and current during load change (Vo = 250 V/div; Io = 1 A/div; time = 20 ms/div).
The measured power factor curves versus output power with different input voltages and versus input voltage with different output powers are shown in Fig. 7(b). The power factors are greater than 0.9 under all conditions. This result reveals that a high power factor is achieved. The measured efficiency curves versus output power with different topologies are shown Fig. 7(c). Given that the traditional topologies shown in Figs. 1(a), 1(b), and 1(c) are operated under hard-switching conditions, the efficiencies of topologies with soft-switching technique, which include the proposed rectifier and the topologies in [16] and [17], are higher than the efficiencies of traditional topologies shown in Figs. 1(a), 1(b), and 1(c). Fig. 7(c) shows the experimental results for verification. Moreover, conduction losses in the proposed rectifier are less than those in the topologies with soft-switching technique [16], [17]. The efficiency of the proposed rectifier is higher than the efficiency of the topologies in [16] and [17], which can also be verified from the experimental results shown in Fig. 7(c). The transient waveforms of the output voltage and current during load change are shown in Fig. 7(d), which reveals that the effect of load changing on the output voltage is small. Thus, the dynamic characteristic of the proposed rectifier is good.
V. CONCLUSION
A high-performance rectifier is proposed in this study. A prototype circuit of the proposed rectifier has been implemented. The proposed rectifier has the following characteristics:
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