JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A Study on Contact Resistance Reduction in Ni Germanide/Ge using Sb Interlayer

  • Kim, Jeyoung (Dep. Electronics Engineering, Chungnam National Univ.) ;
  • Li, Meng (Dep. Electronics Engineering, Chungnam National Univ.) ;
  • Lee, Ga-Won (Dep. Electronics Engineering, Chungnam National Univ.) ;
  • Oh, Jungwoo (Dep. School of Integrated Technology, Yonsei Univ.) ;
  • Lee, Hi-Deok (Dep. Electronics Engineering, Chungnam National Univ.)
  • Received : 2015.08.25
  • Accepted : 2015.12.06
  • Published : 2016.04.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, the decrease in the contact resistance of Ni germanide/Ge contact was studied as a function of the thickness of the antimony (Sb) interlayer for high performance Ge MOSFETs. Sb layers with various thickness of 2, 5, 8 and 12 nm were deposited by RF-Magnetron sputter on n-type Ge on Si wafers, followed by in situ deposition of 15nm-thick Ni film. The contact resistance of samples with the Sb interlayer was lower than that of the reference sample without the Sb interlayer. We found that the Sb interlayer can lower the contact resistance of Ni germanide/Ge contact but the reduction of contact resistance becomes saturated as the Sb interlayer thickness increases. The proposed method is useful for high performance n-channel Ge MOSFETs.

Keywords

References

  1. C. Claeyes et al, Germanium-Based Technology: From Materials to Devices, Elsevier, 2007.
  2. M. Koike et al, "Diffusion and activation of n-type dopants in germanium," J. Appl. Phys., Vol. 104, pp. 023523-1-5, 2008. https://doi.org/10.1063/1.2958326
  3. A. Dimoulas et al, "Fermi-level pinning and charge neutrality level in germanium," Appl. Phys. Lett., Vol. 89, pp. 052110-1-5, 2006. https://doi.org/10.1063/1.2236300
  4. P. Tsipas et al, "Modeling of negatively charged states at the Ge surface and interfaces," Appl. Phys. Lett., Vol. 94, pp. 012114-1-5, 2009. https://doi.org/10.1063/1.3068497
  5. M. Li et al, "Improvement of Thermal Stability of Nickel Silicide Using Co-sputtering of Ni and Ti for Nano-Scale CMOS Technology," J. Semicond. Technol. Sci., Vol. 13, No. 3, pp. 252-258, 2013. https://doi.org/10.5573/JSTS.2013.13.3.252
  6. H. S. Shin et al, "Improvement of Thermal Stability of Ni-Germanide with Ni/Co/Ni/TiN Structure," Jpn. J. Appl. Phys., Vol. 51, pp. 02BA02-1-3, 2012. https://doi.org/10.7567/JJAP.51.02BA02
  7. S. D. Kim et al, "Advanced Model and Analysis of Series Resistance for CMOS Scaling In to Nanometer Regime - Part II: Quantitative analysis," IEEE Transactions on Electron Devices, Vol. 49, No. 3, pp. 467 - 472. 2002. https://doi.org/10.1109/16.987118
  8. J. A. Kittl et al, "Self-aligned Ti and Co silicides for high performance sub-0.18um CMOS technology," Thin Solids Films, Vol. 320, pp. 110-121, 1998. https://doi.org/10.1016/S0040-6090(97)01069-9
  9. S. D. Kim et al, "Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime-Part I: Theoretical Derivation," IEEE Transactions on Electron Devices, Vol. 49, No. 3, pp. 457-466. 2002. https://doi.org/10.1109/16.987117
  10. R. K. Mishra et al, "Nickel germanide with rare earth interlayers for Ge CMOS applications," 2013 IEEE international Conference of Electron Devices and Solid-State Circuits, EDSSC 2013, , 2013, p. 1-2.
  11. K. Scheroder, SEMICONDUCTOR MATERIAL AND DEVICE CHARACTERIZATION, Wiley-Interscience, 2006.
  12. M.Shayesteh et al, "NiGe contacts and Junction Architectures for P and As Doped Germanium Devices,", IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp. 3801 - 3807, Nov, 2011. https://doi.org/10.1109/TED.2011.2164801