한국인터넷방송통신학회논문지 (The Journal of the Institute of Internet, Broadcasting and Communication)

  • 제16권1호
  • /
  • Pages.233-238
  • /
  • 2016
  • /
  • 2289-0238(pISSN)
  • /
  • 2289-0246(eISSN)
한국인터넷방송통신학회 (The Institute of Internet, Broadcasting and Communication)
권호 표지
DOI QR코드

DOI QR Code

비대칭적 임베디드 멀티코어 프로세서의 성능 연구

A Performance Study of Asymmetric Embedded Multi-Core Processors

  • 이종복 (한성대학교 정보통신공학과)
  • 투고 : 2015.12.02
  • 심사 : 2016.02.05
  • 발행 : 2016.02.29
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

근래에 임베디드 프로세서의 성능을 향상시키기 위하여 멀티코어 프로세서 구조가 널리 이용되고 있다. 이러한 멀티코어 프로세서는 크게 대칭적 구조와 비대칭적 구조로 나뉘며, 비대칭적 멀티코어 프로세서가 대칭적 멀티코어 프로세서에 비하여 더욱 성능이 높고 효율적이라고 알려져 있다. 본 논문에서는 임베디드 프로세서에 대하여 이것을 확인하기 위하여, 다양한 구성을 갖는 비대칭적 임베디드 듀얼코어, 쿼드코어, 옥타코어 및 헥사데카코어 프로세서에 대하여 MiBench 벤치마크를 입력으로 하여 모의실험을 수행하여 그 성능을 측정하였다. 또한, 비슷한 하드웨어 규모의 대칭적 임베디드 멀티코어 프로세서와 비교하여 성능의 우수성을 확인하였다.

Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.

키워드

참고문헌

  1. J. Balfour et. al, "An Energy-Efficient Processor Architecture for Embedded Systems," IEEE Computer Architectures, Vol. 7, No. 1, Jun. 2008.
  2. J. Lee, "A Performance Study of Embedded Multicore Processor Architectures," Journal of The Institute of Internet, Broadcasting and Communication, vol. 13, no. 1, pp. 163-169, Feb. 2013. https://doi.org/10.7236/JIIBC.2013.13.1.163
  3. R. Kumar et al, "Single-ISA heterogeneous Multicore Architectures for Heterogeneous for Multithreaded Workload Performance," Annual International Symposium on Computer Architecture, Mar. 2004.
  4. Hourd, Jon, et al. "Exploring Practical Benefits of Asymmetric Multicore Processors," Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures, Apr. 2009.
  5. T. Ungerer, B. Robic, and J. Silk, "Multithreaded Processors," The Computer Journal, Vol. 45, No. 3, 2002
  6. G. S. Sohi, S. E. Breach, and T. N. Vijaykumar, "Multiscalar Processors," Proceedings of the 22nd annual international symposium on Computer architecture, pp. 414-425, May 1995.
  7. T-Y. Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," in Proceedings of the 19th International Symposium on Computer Architecture, pp.124-134, May. 1992.
  8. J. Lee, "A Study of Trace-driven Simulation for Multi-core Processor Architectures," Journal of The Institute of Internet, Broadcasting and Communication, vol. 12, no. 3, pp. 9-13, Jun. 2012.
  9. M. R. Guthaus, J. S. Ringenberg, D. Ernest, T. M. Austin, T. Mudge, and R. B. Brown, "MiBench: A free, commercial representative embedded benchmark suite," Workload Characterization, pp. 3-14, Dec. 2001.
  10. T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002. https://doi.org/10.1109/2.982917