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Efficient VLSI Architecture of Full-Image Guided Filter Based on Two-Pass Model

양방향 모델을 적용한 Full-image Guided Filter의 효율적인 VLSI 구조

  • Lee, Gyeore (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea) ;
  • Park, Taegeun (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea)
  • Received : 2016.09.02
  • Accepted : 2016.11.07
  • Published : 2016.11.30

Abstract

Full-image guided filter reflects all pixels of image in filtering by using weight propagation and two-pass model, whereas the existing guide filter is processed based on the kernel window. Therefore the computational complexity can be improved while maintaining characteristics of guide filter, such as edge-preserving, smoothing, and so on. In this paper, we propose an efficient VLSI architecture for the full-image guided filter by analyzing the data dependency, the data frequency and the PSNR analysis of the image in order to achieve enough speed for various applications such as stereo vision, real-time systems, etc. In addition, the proposed efficient scheduling enables the realtime process by minimizing the idle period in weight computation. The proposed VLSI architecture shows 214MHz of maximum operating frequency (image size: 384*288, 965 fps) and 76K of gates (internal memory excluded).

Full-image guided filter는 커널 윈도우 영역만 필터링에 반영되는 기존의 커널 윈도우 기반 가이드 필터와 달리 가중치 전파 도식과 양방향 모델이 적용되어 영상의 모든 픽셀이 필터링에 반영된다. 이로써 가이드 필터의 경계 보존과 평활화 등의 가이드 이미지 필터의 특성을 유지하면서도 계산 복잡도를 개선할 수 있다. 본 논문에서는 full-image guided filter의 더 빠른 처리가 필요한 스테레오 비전 및 각종 실시간 시스템 분야에 적용될 수 있도록 효율적인 하드웨어 구조를 제안하였다. 필터링 프로세스에서 발생하는 각종 데이터의 종속성 분석과 영상의 PSNR 분석, 데이터 빈도 분석 등을 통하여 적합한 하드웨어 구조를 제안하였다. 또한 양방향 모델이 적용된 가중치 연산 모듈의 휴식 구간이 최소화되도록 효율적인 스케줄링을 하였고 실시간 처리가 가능하게 하였다. 제안한 하드웨어 구조는 동부하이텍 0.11um 표준셀 라이브러리로 합성하였을 경우 최대 동작주파수 214MHz(384*288 영상: 965 fps)와 76K(내부 메모리 제외) 게이트의 하드웨어 복잡도를 나타냈다.

Keywords

References

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