Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Low Jitter Dual Output Frequency Synthesizer Using Phase-Locked Loop for Smart Audio Devices

위상고정루프를 이용한 낮은 지터 성능을 갖는 스마트 오디오 디바이스용 이중 출력 주파수 합성기 설계

  • Baek, Ye-Seul (Electrical and Electronic Engineering, Chung-Ang University) ;
  • Lee, Jeong-Yun (Electrical and Electronic Engineering, Chung-Ang University) ;
  • Ryu, Hyuk (Electrical and Electronic Engineering, Chung-Ang University) ;
  • Lee, Jongyeon (Electrical and Electronic Engineering, Chung-Ang University) ;
  • Baek, Donghyun (Electrical and Electronic Engineering, Chung-Ang University)
  • 백예슬 (중앙대학교 전자전기공학부) ;
  • 이정윤 (중앙대학교 전자전기공학부) ;
  • 류혁 (중앙대학교 전자전기공학부) ;
  • 이종연 (중앙대학교 전자전기공학부) ;
  • 백동현 (중앙대학교 전자전기공학부)
  • Received : 2015.10.14
  • Accepted : 2016.01.15
  • Published : 2016.02.25
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Abstract

A Low jitter dual output frequency synthesizer for smart audio devices is described in this paper. It has been fabricated in a 1.8 V Dongbu $0.18-{\mu}m$ CMOS process. Output frequency is controlled by 3 rd order Sigma-Delta Modulation and digital divider. The frequency synthesizer has a size of $0.6mm^2$, frequency range of 0.6-200 MHz, loop bandwidth of 350 kHz, and rms jitter of 11.4 ps-21.6 ps.

본 논문에서는 위상고정루프를 이용한 낮은 지터 성능을 갖는 스마트 오디오 디바이스용 이중출력 주파수 합성기를 제안하였다. 제안하는 주파수 합성기는 1.8 V 동부 $0.18-{\mu}m$ CMOS 공정을 이용하여 설계하였다. 다양한 오디오 샘플링 주파수를 출력하기 위해 3차 시그마-델타 모듈레이션을 이용하여 fraction-N 디바이더를 설계하였다. 오디오 반도체에서 요구되는 낮은 지터 성능을 만족 시키기 위해 인-밴드 잡음을 분석, 최적화 하였다. $0.6mm^2$의 칩 사이즈를 가지고 0.6 MHz-200 MHz의 출력 주파수를 갖는다. 모든 모드에서 측정된 지터는 11.4 ps-21.6 ps 이다.

Keywords

References

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