JSTS:Journal of Semiconductor Technology and Science

  • 제16권6호
  • /
  • Pages.873-879
  • /
  • 2016
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

A CMOS Charge Pump Circuit with Short Turn-on Time for Low-spur PLL Synthesizers

  • Sohn, Jihoon (Dept. of Radio Science and Engineering, Kwangwoon University) ;
  • Shin, Hyunchol (Dept. of Radio Science and Engineering, Kwangwoon University)
  • 투고 : 2016.08.25
  • 심사 : 2016.11.18
  • 발행 : 2016.12.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is $490{\mu}A$ from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.

키워드

참고문헌

  1. W. Rhee, "Design of high-performance CMOS charge pumps in phase-locked loops,", IEEE Int. Symp. on Circuits and Systems, vol. 2, pp. 545-548, May 1999.
  2. N. Kamal, S. Al-Sarawi, and D, Addott, "An Accurate Analytical Spur Model for an Integer-N Phase-Locked Loop," Int. Conf. on Intelligent and Advanced Systems, vol. 2, pp. 659-664, Jun. 2012.
  3. D. Mandal, P. Mandal, and T. K. Bhattacharyya, "Prediction of reference spur in frequency synthesisers," IET Circuits, Devices & Systems, vol 9, no. 2, pp. 131-139, 2015. https://doi.org/10.1049/iet-cds.2014.0019
  4. K. Shu and E. Sanchez-Sinencio, CMOS PLL Synthesizers, Boston, MA, Springer 2005.
  5. P. Larsson, "A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability," IEEE J. of Solid-State Circuits, vol. 34, no. 12, pp. 1951-1960, Dec. 1999. https://doi.org/10.1109/4.808920
  6. J. M. Ingino, "A 4GHz 40dB PSRR PLL for an SOC Application," IEEE Int. Solid-State Circuits Conf., Dig., pp. 392-393, Feb. 2001.
  7. K. D. Feng and J. C. Lee, "Spark current in charge pump of phase lock loop," IEEE Custom Integrated Circuits Conf., pp. 199-202, Sept. 2005
  8. M. Peng, M. Hossain, W. A. Davis, H. T. Russell, and R. L. Carter, "A 1-V Quasi Rail-to-Rail Operational Amplifier with a Single Input Differential Pair," IEEE Region Five Technical Conf., pp. 93-96, Apr. 2007
  9. Linear Technology, Application Note 143, pp. 1-8.
  10. C.-F. Liang, S.-H. Chen, and S.-I. Liu, "A digital calibration technique for charge pumps in phaselocked systems," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 390-398, Feb. 2008. https://doi.org/10.1109/JSSC.2007.914283
  11. M. M. Elsayed, et al., "A Spur-Frequency-Boosting PLL With a-74 dBc Reference-Spur Suppression in 90 nm Digital CMOS," IEEE J. Solid-State Circuits, vol. 48, no. 9, pp. 2104-2117, Jul. 2013. https://doi.org/10.1109/JSSC.2013.2266865
  12. J. Shin, J. Kim, S. Kim, and H. Shin, "A Delta-Sigma Fractional-N Frequency Synthesizer for Quad-Band Multi-Standard Mobile Broadcasting Tuners in 0.18-${\mu}m$ CMOS," J. of Semiconductor Technology and Science, vol. 7, no 4, pp. 267-273, Dec. 2007. https://doi.org/10.5573/JSTS.2007.7.4.267