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A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

  • Kim, Sungwoo (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Jang, Sungchun (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Cho, Sung-Yong (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Choo, Min-Seong (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Jeong, Gyu-Seob (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Bae, Woorham (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Jeong, Deog-Kyoon (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University)
  • Received : 2016.06.08
  • Accepted : 2016.09.26
  • Published : 2016.12.30

Abstract

An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a $285-fs_{rms}$ integrated jitter at GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is -242.4 dB.

Keywords

References

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  1. A 2.5–5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection vol.65, pp.9, 2018, https://doi.org/10.1109/TCSI.2018.2799195