JSTS:Journal of Semiconductor Technology and Science

  • 제16권6호
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  • Pages.736-744
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  • 2016
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Performance Analysis of Shared Buffer Router Architecture for Low Power Applications

  • Deivakani, M. (Department of ECE, PSNA College of Engineering and Technology) ;
  • Shanthi, D. (Department of CSE, PSNA College of Engineering and Technology)
  • 투고 : 2016.01.06
  • 심사 : 2016.04.24
  • 발행 : 2016.12.30
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초록

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

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참고문헌

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