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Design and Implementation of 256-Point Radix-4 100 Gbit/s FFT Algorithm into FPGA for High-Speed Applications

  • Polat, Gokhan (Department of Electronics and Telecommunication Engineering, Faculty of Engineering, Kocaeli University) ;
  • Ozturk, Sitki (Department of Electronics and Telecommunication Engineering, Faculty of Engineering, Kocaeli University) ;
  • Yakut, Mehmet (Department of Electronics and Telecommunication Engineering, Faculty of Engineering, Kocaeli University)
  • Received : 2014.06.08
  • Accepted : 2015.03.19
  • Published : 2015.08.01
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Abstract

The third-party FFT IP cores available in today's markets do not provide the desired speed demands for optical communication. This study deals with the design and implementation of a 256-point Radix-4 100 Gbit/s FFT, where computational steps are reconsidered and optimized for high-speed applications, such as radar and fiber optics. Alternative methods for FFT implementation are investigated and Radix-4 is decided to be the optimal solution for our fully parallel FPGA application. The algorithms that we will implement during the development phase are to be tested on a Xilinx Virtex-6 FPGA platform. The proposed FFT core has a fully parallel architecture with a latency of nine clocks, and the target clock rate is 312.5 MHz.

Keywords

References

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