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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Design of Multi-time Programmable Memory for PMICs

  • Kim, Yoon-Kyu (Department of Intelligent Machinery System, Pusan National University) ;
  • Kim, Min-Sung (Department of Electronic Engineering, Changwon National University) ;
  • Park, Heon (Department of Electronic Engineering, Changwon National University) ;
  • Ha, Man-Yeong (Department of Intelligent Machinery System, Pusan National University) ;
  • Lee, Jung-Hwan (Department of NVM Device, Magnachip Semiconductor) ;
  • Ha, Pan-Bong (Department of Electronic Engineering, Changwon National University) ;
  • Kim, Young-Hee (Department of Electronic Engineering, Changwon National University)
  • Received : 2015.01.15
  • Accepted : 2015.07.22
  • Published : 2015.12.01
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Abstract

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

Keywords

References

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