차세대 저전력 터널링 트랜지스터

  • 최송헌 (서강대학교 전자공학과) ;
  • 최우영 (서강대학교 전자공학과)
  • Published : 2015.07.25

Abstract

Keywords

References

  1. K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Buechler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. Mchlntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Schifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", Int. Electron Devices Meeting Technical Dig., IEDM 2007, pp. 247-250, 2007.
  2. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King Liu, J. Bokor, and C. Hu, "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm", IEEE Trans. Electron Devices, vol. 47, pp. 2320-2325, 2000. https://doi.org/10.1109/16.887014
  3. P. Packan, "Device and Circuit Interactions," Int. Electron Devices Meeting., IEDM 2008, Short Course: Performance Boosters for Advanced CMOS Devices.
  4. K. J. Kuhn, M. D. Giles, D. Becher, P. Kolar, A. Kornfeld, R. Kotlyar, S. T. Ma, A. Maheshwari, and S. Mudanai, "Process Technology Variation", IEEE Trans. on Elec. Dev., vol. 58, pp. 2197-2208, 2011
  5. T. Hiramoto, "Measurements and Characterization of Statistical Variability", International Conference on Simulation of Semiconductor Processes and Devices, SISPAD workshop 2010.
  6. J.-S. Jang, H. K. Lee, and W. Y. Choi, "Random Dopant Fluctuation Effects of Tunneling Field-Effect Transistors (TFETs)", Journal of the Institute of Electronics Engineers of Korea, vol. 49, pp. 179-183, 2012.
  7. H. Dadgour, E. Kazuhiko, V. De, and K. Banerjee, "Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors-Part I: Modeling, Analysis, and Experimental Validation", IEEE Trans. Electron Devices, vol. 57, pp. 2504-2514, 2010. https://doi.org/10.1109/TED.2010.2063191
  8. K. M. Choi, and W. Y. Choi, "Work-Function Variation Effects of Tunneling Field-Effect Transistors (TFETs)", IEEE Electron Device Letters, vol. 34, pp. 942-944, 2013 https://doi.org/10.1109/LED.2013.2264824