참고문헌
- J. L. Leila, "Numerical Analysis of Thermomechanical Reliability of Through Silicon Vias (TSVs) and Solder Interconnects in 3-dimensional Integrated Circuits", Microelectron. Eng., 87(2), 208 (2010). https://doi.org/10.1016/j.mee.2009.07.022
- D. H. Park, D. M. Jung, and T. S. Oh, "Warpage Characteristics Analysis for Top Packages of Thin Package-on-Packages with Progress of Their Process Steps", J. Microelectron. Packag. Soc., 21(2), 65 (2014). https://doi.org/10.6117/kmeps.2014.21.2.065
- N. Vijayaragavan, F. Carson, and A. Mistry, "Package on Package Warpage - Impact on Surface Mount Yields and Board Level Reliability", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 389, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008).
- H. Eslampour, Y. C. Kim, S. W. Park, T., and W. Lee, "Low Cost Cu Column fcPoP Technology", Proc. 62nd Electronic Components and Technology Conference (ECTC), San Diego, 871, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2012).
- F. Roa, "Very Thin POP and SIP Packaging Approaches to Achieve Functionality Integration prior to TSV Implementation", Proc. 64th Electronic Components and Technology Conference (ECTC), Orlando, 1656, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2014).
- C. G. Kim, H. S. Choi, M. S. Kim, and T. S. Kim, "Packaging Substrate Bending Prediction due to Residual Stress", J. Microelectron. Packag. Soc., 20(1), 21 (2013). https://doi.org/10.6117/kmeps.2013.20.1.021
- J. Zhao, Y. Luo, Z. Huang, and R. Ma, "Effects of Package Design on Top PoP Package Warpage", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1081, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008).
- C. H. Chien, Y. C. Chen, Y. T. Chio, T. Chen, C. C. Hsieh, J. J. Yan, W. Z Chen, and Y. D. Wua, "Influences of the Moisture Absorption on PBGA Package's Warpage during IR Reflow Process", Microelectron. Reliab., 43(1), 131 (2003). https://doi.org/10.1016/S0026-2714(02)00283-4
- G. Kelly, C. Lyden, W. Lawton, J. Barrett, A. Saboui, H. Pape, and H. Peters, "The Importance of Molding Compound Chemical Shrinkage in the Stress and Warpage Analysis of PQFPs", Proc. 45th Electronic Components and Technology Conference (ECTC), Las Vegas, 296, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (1996).
- M. J. Yim, R. Strode, R. Adimula, J. J. Zhang and C. Yoo, "Ultra Thin Top Package using Compression Mold: Its Warpage Control", Proc. 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1141, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2011).
- W. D. van Driel, G. Q. Zhang, J. H. J. Janssen, L. J. Ernst, F. Su, K. S. Chian, and S. Yi, "Prediction and verification of process-induced warpage of electronic packages", Microelectron. Reliab., 43(5), 765 (2003). https://doi.org/10.1016/S0026-2714(03)00057-X
- C. Chiu, K. C. Chang, J. Wang, C. H. Lee, K. Shen, and L. Wang, "Challenges of Thin Core Substrate Flip Chip Package on Advanced Si Nodes", Proc. 57th Electronic Components and Technology Conference (ECTC), Reno, 22, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2007).
- B. H. Lee, M. K. Kim, and J. W. Joo, "Thermo-Mechanical Behavior of WB-PBGA Packages with Pb-Sn Solder and Lead-Free Solder Using Moire Interferometry", J. Microelectron. Packag. Soc., 17(3), 17 (2010).
- JEDEC Standard JESD22-B112A, "Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature", JEDEC Solid State Technology Association, Arlington (2009).
- M. J. Yim, R. Strode, R. Adimula, and C. Yoo, "Effects of Material Properties on PoP Top Package Warpage Behaviors", Proc. 60th Electronic Components and Technology Conference (ECTC), Las Vegas, 1071, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2010).
- S. Michaelides and S. K. Sitaraman, "Die Cracking and Reliable Die Design for Flip-Chip Assemblies", IEEE Transactions on Advanced Packaging, 22(4), 602 (1999). https://doi.org/10.1109/6040.803452
- Y. Sawada, K. Harada, and H. Fujioka, "Study of Package Warpage Behavior for High-Performance Flip-Chip BGA", Microelectron. Reliab., 43(3), 465 (2003). https://doi.org/10.1016/S0026-2714(02)00294-9
- N. Boyard, A. Millischer, V. Sobotka, J. Bailleul, and D. Delaunay, "Behaviour of a Moulded Composite Part: Modelling of Dilatometric Curve (Constant Pressure) or Pressure (Constant Volume) with Temperature and Conversion Degree Gradients", Composite Sci. Technol., 67(6), 943 (2007). https://doi.org/10.1016/j.compscitech.2006.07.004
- S. Y. Yang, Y. Jeon, S. Lee, and K. Paik, "Solder Reflow Process Induced Residual Warpage Measurement and Its Influence on Reliability of Flip-Chip Electronic Packages", Microelectron. Reliab., 46(2), 512 (2006). https://doi.org/10.1016/j.microrel.2005.06.007
- S. H. Cho, T. E. Chang, J. Y. Lee, H. P. Park, Y. Ko, and G. Park, "New Dummy Design and Stiffener on Warpage Reduction in Ball Grid Array Printed Circuit Board", Microelectron. Reliab., 50(2), 242 (2010). https://doi.org/10.1016/j.microrel.2009.10.009
피인용 문헌
- Reliability Characteristics of a Package-on-Package with Temperature/Humidity Test, Temperature Cycling Test, and High Temperature Storage Test vol.23, pp.3, 2016, https://doi.org/10.6117/kmeps.2016.23.3.043