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3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook (New Industry Creation hatchery Center, Tohoku University)
  • Received : 2015.06.10
  • Accepted : 2015.06.26
  • Published : 2015.06.30

Abstract

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Keywords

References

  1. M. Koyanagi, "Roadblocks in Achieving Three-Dimensional LSI", Proc. 8th Symposium on Future Electron Devices, 50 (1989).
  2. T. Kunio, K. Oyama, Y. Hayashi and M. Morimoto, "Three dimensional ICs, having four stacked active device layers", International Electron Devices Meeting (IEDM), Washington, DC, USA, 837, IEEE (1989).
  3. M. Koyanagi, H. Kurino, K. W. Lee, K. Sakuma, N. Miyakawa and H. Itani, "Future system-on-silicon LSI chips", IEEE MICRO, 18(4), 17 (1998). https://doi.org/10.1109/40.710867
  4. S. J. Souri, K. Banerjee, A. Mehrotra and K. C. Saraswat, "Multiple Si layer ICs: Motivation, performance analysis, and design implications", Proc. 37th ACM Design Automation Conf., NY, USA, 873 (2000).
  5. K. Banerjee, S. J. Souri, P. Kapur and K. C. Saraswat, "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration", Proceedings of the IEEE, 89(5), 602 (2001). https://doi.org/10.1109/5.929647
  6. P. Ramm, D. Bonfert, H. Gieser, J. Haufe, F. Iberl, A. Klumpp, A. Kux and R. Wieland, "Interchip via technology for vertical system integration", Proc. International Interconnect Technology Conference (IITC), Burlingame, CA, USA, 160, IEEE (2001).
  7. K. W. Lee, "The next generation package technology for higher performance and smaller systems", Proc. 3rd Int. Conf. 3D Architect. Semicond. Integr. Packag. (2006).
  8. J.-Q. Lu, K. Rose and S. Vitkavage, "3D Integration: Why, what, who, when?", Future Fab International, 23, 25 (2007).
  9. A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D'Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. Dahringer, L. M. F. Chirovsky and D. A. B. Miller, "3-D Integration of MQW Modulators Over Active Submicron CMOS Circuits: 375 Mb/s Transimpedance Receiver-Transmitter Circuit", Photonics Technology Letters, 7(11), 1288, IEEE (1995). https://doi.org/10.1109/68.473474
  10. P. Dainesi, A. M. Ionescu, L. Thevenaz, K. Banerjee, M. J. Declercq, P. Robert, P. Renaud, P. Fluckiger, C. Hilbert and G. A. Racine, "3-D Integration Optoelectronics Devices for Telecommunication ICs", Int. Solid State Circuits Conference (ISSCC), 290, IEEE (2002).
  11. A. Mekis, S. Abdalla, B. Analui, S. Gloeckner, A. Guckenberger, K. Koumans, D. Kucharski, Y. Liang, G. Masini, S. Mirsaidi, A. Narasimha, T. Pinguet, V. Sadagopan, B. Welch, J. White and J. Witzens, "Monolithic Integration of Photonic and Electronic Circuits in a CMOS Process", Proc. SPIE 6897, Optoelectronic Integrated Circuits X, San Jose, CA, 68970L (2008).
  12. Y. Vlasov, W. M. Green and F. Xia, "High-throughput silicon nanophotonic deflection switch for on-chip optical networks", Optical Fiber Communication Conference, San Diego, CA, 24, Optical Society of America (OSA) (2008).
  13. T. C. Chen, "Device Technology Innovation for Exascale Computing", Proc. VLSI Technology Symposium, Honolulu, HI, 8, IEEE (2009).
  14. M. J. Wolf, P. Ramm, A. Klumpp and H. Reichl, "Technologies for 3D Wafer Level Heterogeneous Integration", Design, Test, Integration and Packaging of MEMS/MOEMS, Nice, 123, IEEE (2008).
  15. Y. A. Chapuis, A. Debray, L. Jalabert and H. Fujita, "Alternative approach in 3D MEMS-IC integration using fluidic self-assembly techniques", J. Micromech. Microeng., 19(10), 105002 (2009). https://doi.org/10.1088/0960-1317/19/10/105002
  16. N. Sillon, D. Henry, J. C. Souriau, J. Brun, H. Boutry and S. Cheramy, "New trends in wafer level packaging", Proc. International Interconnect Technology Conference (IITC), Sapporo, Hokkaido, 211, IEEE (2009).
  17. K. W. Lee, "Ultimate Heterogeneous Integration Technology for Super-chip", J. Microelectron. Packag. Soc., 17(4), 1 (2010).
  18. T. Fukushima, H. Kikuchi, Y. Yamada, T. Konno, J. Liang, K. Sasaki, K. Inamura, T. Tanaka and M. Koyanagi, "New three-dimensional integration technology based on reconfigured wafer-on-wafer bonding technique", International Electron Devices Meeting (IEDM), Washington, DC, 985, IEEE (2007).
  19. T. Fukushima, E. Iwata, Y. Ohara, A. Noriki, K. Inamura, K. W. Lee, J. Bea, T. Tanaka and M. Koyanagi, "Three-Dimensional Integration Technology Based on Reconfigured Wafer-to-Wafer Stacking Using Self-Assembly Method", International Electron Devices Meeting (IEDM), Baltimore, MD, 349, IEEE (2009).
  20. T. Fukushima, Y. Ohara, J. Bea, M. Murugesan, K. W. Lee, T. Tanaka and M. Koyanagi, "Non-Conductive Film and Compression Molding Technology for Self-Assembly-Based 3D Integration", Electronic Components and Technology Conference (ECTC), San Diego, CA, 393, IEEE (2012).
  21. T. Fukushima, H. Hashiguchi, J. Bea, M. Murugesan, K.-W Lee, T. Tanaka and M. Koyanagi, "3D Integration technologies using self-assembly and electrostatic temporary multichip bonding", Electrical Components Technology Conference (ECTC), Las Vegas, NV, 58, IEEE (2013).
  22. J. Engstrom, J. Arfwidsson, A. Amditis, L. Andreone, K. Bengler, P. C. Cacciabue, J. Eschler, F. Nathan and W. Janssen, "Meeting the Challenges of Future Automotive HMI Design: Overview of the AIDE Integrated Project", Proc. 4th European Congress on Intelligent Transportation Systems and Services (ITS), Budapest, Hungary (2004).
  23. K.-W. Lee, A. Noriki, K. Kiyoyama, S. Kanno, R. Kobayashi, W.-C Jeong, J.-C. Bea, T. Fukushima, T. Tanaka and M. Koyanagi, "3D Heterogeneous Opto-Electronic Integration Technology for System-on-Silicon (SOS)", International Electron Devices Meeting Technical Digest (IEDM), Baltimore, MD, 1, IEEE (2009).
  24. K.-W. Lee, A. Noriki, K. Kiyoyama, T. Fukushima, T. Tanaka and M. Koyanagi, "Three-Dimensional Hybrid Integration Technology of CMOS, MEMS and Photonic Circuits for Opto-Electronic Heterogeneous Integrated Systems", Electron Devices, 58(3), 748, IEEE (2011). https://doi.org/10.1109/TED.2010.2099870
  25. K.-W. Lee, S. Kanno, Y. Ohara, K. Kiyoyama, J.-C. Bea, T. Fukushima, T. Tanaka, and M. Koyanagi, "Novel interconnection technology for heterogeneous integration of MEMS-LSI multi-chip module", Microsystem Technologies, 16(3), 441 (2010). https://doi.org/10.1007/s00542-009-0941-z
  26. K.-W. Lee, S. Kanno, K. Kiyoyama, T. Fukusima, T. Tanaka and M. Koyanagi, "A Cavity Chip Interconnection Technology for Thick MEMS Chip Integration in MEMS-LSI Multi-Chip Module", IEEE Journal of Microelectromechanical Systems, 19(6), 1284 (2010). https://doi.org/10.1109/JMEMS.2010.2082497
  27. A. Noriki, K.-W. Lee, J.-C. Bae, T. Fukushima, T. Tanaka and M. Koyanagi, "Through-Silicon Photonic Via and Unidirectional Coupler for High-Speed Data Transmission in Optoelectronic 3-D LSI", IEEE Electron Device Letters, 33(2), 221 (2012). https://doi.org/10.1109/LED.2011.2174608
  28. K.-W. Lee, Y. Ohara, K. Kiyoyama, S. Konno, Y. Sato, S. Watanabe, A. Yabata, T. Kamada, J.-C Bea, H. Hashimoto, M. Murugesan, T. Fukushima, T. Tanaka and M. Koyanagi, "Characterization of Chip-level Hetero-Integration Technology for High-Speed, Highly Parallel 3D Stacked Image Processing System", IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 785, IEEE (2012).
  29. K.-W. Lee, H. Hashimoto, M. Onishi, Y. Sato, M. Murugesan, J.-C Bae, T. Fukushima, T. Tanaka and M. Koyanagi, "A Resilient 3-D Stacked Multicore Processor Fabricated Using Die-Level 3-D Integration and Backside TSV Technologies", IEEE 64th Electronic Components and Technology Conference (ECTC), Orlando, FL, 304 (2014).
  30. K. Kiyoyama, Y. Ohara, K.-W. Lee, T. Fukushima, T. Tanaka and M. Koyanagi, "A Parallel ADC for High Speed CMOS Image Processing System with 3D Structure", IEEE International 3D System Integration Conference (3DIC), San Francisco, CA, 1, IEEE (2009).
  31. K.-W. Lee, Y. Ohara, K. Kiyoyama, J.-C. Bea, M. Murugesan, T. Fukushima, T. Tanaka and M. Koyanagi, "Die-level 3-D Integration Technology for Rapid Prototyping of High Performance, Multi Functionality Hetero-Integrated Systems", IEEE Transactions on Electron Devices, 60(11), 3842, IEEE (2013). https://doi.org/10.1109/TED.2013.2280273
  32. H. Hashimoto, T. Fukushima, K.-W. Lee, M. Koyanagi and T. Tanaka, "Highly Efficient TSV Repair Technology for Resilient 3-D Stacked Multicore Processor System", IEEE International 3D System Integration Conference (3DIC), San Francisco, CA, 1, IEEE (2013).
  33. K.-W. Lee, H. Hashimoto, M. Onishi, Y. Sato, C. Nagai, J.-C. Bea, M. Murugesan, T. Fukushima, T. Tanaka and M. Koyanagi, "Highly dependable 3-D stacked multicore processor system module fabricated using reconfigured multichipon-wafer 3-D integration technology", International Electron Devices Meeting (IEDM), San Francisco, CA, 28.6.1, IEEE (2014).
  34. K.-W. Lee, M. Murugesan, J. Bea, T. Fukushima, T. Tanaka and M. Koyanagi, "Characterization and Reliability of 3D LSI and SiP", IEEE International Electron Devices Meeting (IEDM), Washington, DC, 7.2.1, IEEE (2013).
  35. M. S. Park, S. D. Kim and S. E. Kim, "TSV Liquid Cooling System for 3D Integrated Circuits", J. Microelectron. Packag. Soc., 20(3), 1 (2013). https://doi.org/10.6117/KMEPS.2013.20.3.001
  36. J. W. Yoon, J. H. Bang, Y. H. Ko, S. H. Yoo, J. K. Kim and C. W. Lee, "Power Module Packaging Technology with Extended Reliability for Electric Vehicle Applications", J. Microelectron. Packag. Soc., 21(4), 1 (2014). https://doi.org/10.6117/kmeps.2014.21.4.001

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