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Hardware Implementation of HEVC CABAC Context Modeler

HEVC CABAC 문맥 모델러의 하드웨어 구현

  • Kim, Doohwan (School of Electronic Engineering, Soongsil University) ;
  • Moon, Jeonhak (School of Electronic Engineering, Soongsil University) ;
  • Lee, Seongsoo (School of Electronic Engineering, Soongsil University)
  • Received : 2015.06.01
  • Accepted : 2015.06.23
  • Published : 2015.06.30

Abstract

CABAC is a context-based adaptive binary arithmetic coding method. It increases the encoding efficiency by updating the probability based on the information of the previously coded symbols. Context modeler is a core block of CABAC, which designs a probability model according to the symbol considering statistical correlations. In this paper, an efficient hardware architecture of CABAC context modeler is proposed. The proposed context modeler was designed in Verilog HDL and it was implemented in 0.18 um technology. Its gate count is 29,832 gates including memory. Its operating speed and throughput are 200 MHz and 200 Mbin/s, respectively.

CABAC은 문맥 기반 적응적 이진 산술 부호화 방식으로, 이전까지 부호화 된 심볼들의 정보를 이용하여 확률을 업데이트하여 부호화 효율을 높이는 기법이다. 문맥 모델러는 통계적 상관성을 고려하여 심볼에 따라 확률 모델을 설계하는 CABAC의 핵심 블록으로서, 본 논문에서는 문맥 모델러의 효율적인 하드웨어 아키텍쳐를 제안한다. Verilog HDL로 기술되어 0.18 um 공정으로 설계된 문맥 모델러는 메모리를 포함하여 29,832개의 게이트로 이루어져 있으며, 최대 동작속도는 200 MHz, 최대 처리율은 200 Mbin/s이다.

Keywords

References

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Cited by

  1. Design of HEVC CABAC Encoder With Parallel Processing of Bypass Bins vol.19, pp.4, 2015, https://doi.org/10.7471/ikeee.2015.19.4.583