DOI QR코드

DOI QR Code

Study on the Thermal Transient Response of TSV Considering the Effect of Electronic-Thermal Coupling

  • Li, Chunquan (School of Electrical Engineering and Automation, Guilin University of Electronic Technology) ;
  • Zou, Meng-Qiang (School of Electrical Engineering and Automation, Guilin University of Electronic Technology) ;
  • Shang, Yuling (School of Electrical Engineering and Automation, Guilin University of Electronic Technology) ;
  • Zhang, Ming (School of Electrical Engineering and Automation, Guilin University of Electronic Technology)
  • 투고 : 2014.12.09
  • 심사 : 2015.05.29
  • 발행 : 2015.06.30

초록

The transmission performance of TSV considering the effect of electronic-thermal coupling is an new challenge in three dimension integrated circuit. This paper presents the thermal equivalent circuit (TEC) model of the TSV, and discussed the thermal equivalent parameters for TSV. Si layer is equivalent to transmission line according to its thermal characteristic. Thermal transient response (TTR) of TSV considering electronic-thermal coupling effects are proposed, iteration flow electronic-thermal coupling for TSV is analyzed. Furthermore, the influences of TTR are investigated with the non-coupling and considering coupling for TSV. Finally, the relationship among temperature, thickness of $SiO_2$, radius of via and frequency of excitation source are addressed, which are verified by the simulation.

키워드

참고문헌

  1. Lau, J.H., "Through-Silicon Vias for 3D Integration," New York, McGraw-Hill, 2012
  2. Bakir, Muhannad S., et al., "3D heterogeneous integrated systems: liquid cooling, power delivery, and implementation." Custom Integrated Circuits Conference, IEEE, pp.663-670. Sep., 2008
  3. Khan, N. and S. Hassoun, "Designing TSVs for 3D Integrated Circuits," New York, Springer, 2012.
  4. Yang, Ping, and Zixia Chen. "Experimental approach and evaluation on dynamic reliability of PBGA assembly," Electron Devices, IEEE Transactions on 56.10, pp.2243-2249, 2009. https://doi.org/10.1109/TED.2009.2027974
  5. Liu, D. J., et al. "Effect of temperature and voltage on LED luminaries reliability." International Journal of Materials and Structural Integrity, Vol.6(2), pp. 270-283, 2012. https://doi.org/10.1504/IJMSI.2012.049960
  6. Xi, T., et al., "Numerical investigation on the thermal reliability and layout optimization of printed circuit board level," International Journal of Materials and Structural Integrity,. Vol.6(2), pp. 309-318, 2012. https://doi.org/10.1504/IJMSI.2012.049963
  7. Shang, Yuling, et al. "Study on the crosstalk characteristic of non-ideal interconnect structure," International Journal of Materials and Structural Integrity, Vol.7(1), pp.144-159, 2013 https://doi.org/10.1504/IJMSI.2013.055112
  8. Jang, Dong Min, et al. "Development and evaluation of 3-D SiP with vertically interconnected through silicon vias (TSV)," Electronic Components and Technology Conference, 2007, ECTC'07, Proceedings. 57th. IEEE, pp. 847-852, May, 2007
  9. Swift, G., T.S. Molinski and W. Lehn, "A fundamental approach to transformer thermal modeling. I. Theory and equivalent circuit," Power Delivery, IEEE Transactions on, Vol.16(2): pp. 171-175, 2001 https://doi.org/10.1109/61.915478
  10. Lau, John H. "Evolution and outlook of TSV and 3D IC/Si integration," Electronics Packaging Technology Conference, 2010, EPTC, 12th. IEEE, pp. 560-570, 2010
  11. Lau, J. H. "Evolution, challenge, and outlook of TSV, 3D IC integration and 3D silicon integration," Advanced Packaging Materials (APM), 2011 International Symposium on IEEE, pp. 462-488, Oct. 2011
  12. Lau J H. "TSV manufacturing yield and hidden costs for 3D IC integration," Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th. IEEE, pp.1031-1042, June, 2010
  13. Hoe Y Y G, Yue T G, et al. Effect of TSV interposer on the thermal performance of FCBGA package," Electronics Packaging Technology Conference, 2009. EPTC'09. 11th. IEEE, pp.778- 786, Dec. 2009
  14. Ho S W, Yoon S W, Zhou Q, et al. "High RF performance TSV silicon carrier for high frequency application," Electronic Components and Technology Conference, 2008. ECTC 2008. 58th. IEEE, pp.1946-1952, May, 2008
  15. Katti G, Stucchi M, De Meyer K, et al. "Electrical modeling and characterization of through silicon via for three-dimensional Ics," Electron Devices, IEEE Transactions on, pp.256-262, 2010
  16. Cadix L, Farcy A, Bermond C, et al. "Modelling of through silicon via RF performance and impact on signal transmission in 3D integrated circuits," 3D System Integration, 2009. 3DIC 2009. IEEE International Conference on. IEEE, pp.1-7, Sep. 2009
  17. Zhu, Z., Z. Ping and Y. Yintang, "An analytical thermal model for 3D integrated circuit considering through silicon via," Chinese Journal of Physics, Vol.60(11), pp. 118401-118406, 2011
  18. Yan, Z., et al., "Thermal Management of 3D Integrated Circuits Considering Horizontal Heat Transfer Effect," Chinese Journal of Computational Physics, Vol.30(5), pp.753-758, 2013
  19. Matsumoto K, Ibaraki S, Sueoka K, et al. "Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements," Semiconductor Thermal Measurement and Management Symposium (SEMITHERM), 2012 28th Annual IEEE. IEEE, pp.8-13, 2012
  20. Chen Z, Luo X, Liu S. "Thermal analysis of 3D packaging with a simplified thermal resistance network model and finite element simulation," Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), 2010 11th International Conference on IEEE, pp.737-741, 2010
  21. Kannan, S., B. Kim and B. Ahn, "Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects," Journal of Electronic Testing, Vol.28(1), pp. 39-51, 2012 https://doi.org/10.1007/s10836-011-5263-2
  22. Salome P, Leroux C, Crevel P, et al. "Investigations on the thermal behavior of interconnects under ESD transients using a simplified thermal RC network," Microelectronics Reliability, Vol.39(11), pp.1579-1591, 1999 https://doi.org/10.1016/S0026-2714(99)00073-6
  23. Uchino T, Cong J. "An interconnect energy model considering coupling effects," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol.21(7), pp.763-776, 2002 https://doi.org/10.1109/TCAD.2002.1013890
  24. Papanikolaou, A., D. Soudris and R. Radojcic, "Three Dimensional System Integration," New York, Springer, 2011
  25. Li X C, Mao J F, Huang H F. "Accurate analysis of interconnect trees with distributed RLC model and moment matching," Microwave Theory and Techniques, IEEE Transactions on, Vol.52(9): pp.2199-2206, 2004 https://doi.org/10.1109/TMTT.2004.834539
  26. Wang X P, Yin W Y, He S L. "Multiphysics Characterization of Transient Electrothermomechanical Responses of Through-Silicon Vias Applied With a Periodic Voltage Pulse," Electron Devices, IEEE Transactions on, Vol.57(6): pp.1382-1389, 2010 https://doi.org/10.1109/TED.2010.2045676
  27. Xie J Y, Xie B C, Madhavan S. "Electrical-thermal modeling of through-silicon via (TSV) arrays in interposer." International Journal of Numerical Modelling, Vol.26 (6) : pp.545-559, 2013 https://doi.org/10.1002/jnm.1859

피인용 문헌

  1. Morphology-Driven Emissivity of Microscale Tree-like Structures for Radiative Thermal Management vol.22, pp.2, 2018, https://doi.org/10.1080/15567265.2018.1446065