Journal of the Korea Academia-Industrial cooperation Society (한국산학기술학회논문지)

The Korea Academia-Industrial cooperation Society (한국산학기술학회)
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Comparison of Nios II Core-based Accelerators

Niod II 코어기반 가속기 비교

  • Song, Gi-Yong (School of Electronics Engineering, Chungbuk National University)
  • 송기용 (충북대학교 전자공학부)
  • Received : 2014.07.24
  • Accepted : 2015.01.08
  • Published : 2015.01.31
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Abstract

Checksum and residue checking accelerators were implemented on a Nios II core-based platform according to component method, in which the corresponding hardware was implemented with HDL coding, a custom instruction method, in which the instruction set of the processor was extended, and the C2H method, in which the corresponding logic was automatically created by the C2H compiler. The processing results from each accelerator for each algorithm were then examined and compared. The results of the comparison showed that the accelerator implemented with the C2H method is the fastest in terms of the execution time, and the accelerator with custom instruction requires the least add-on from the viewpoint of add-on hardware.

Nios II 코어에 기반한 하드웨어 가속기를 checksum과 residue checking 알고리즘을 대상으로 하여 HDL 코딩으로 해당 하드웨어를 구현하는 component 방식, 프로세서 명령어세트 확장에 의한 custom instruction 방식과 C2H 컴파일러로 해당 로직을 자동 생성하는 C2H 방식으로 구현하고, 실행 결과를 분석 및 비교한다. 비교 결과 실행 소요시간 기준의 경우 C2H 방식 구현이 최단시간 수행을, 그리고 하드웨어 추가 소요량 기준의 경우 custom instruction 방식 구현이 최소의 하드웨어를 추가로 사용함을 확인한다.

Keywords

References

  1. Li Junwei, Yan Han, "The Development of a SOPC system based Nios II," Sciencepaper Online, 2007.
  2. Yu-Chih Liu, M, Hardware objects & accelerators on Nios II platform, Thesis for Master of Science, Department of Computer Science and Engineering ,Tatung University, 2009.
  3. Altera Corporation, "Avalon Interface Specifications," http://www.altera.com/literature/manual/mnl_avalon_spec.pdf,May. 2013.
  4. Altera Corporation, "Nios II Custom Instruction User Guide," http://www.altera.com/literature/ug/ug_nios2_custom_instruction.pdf, January. 2011.
  5. Altera Corporation, "Nios II C2H Compiler User Guide," http://www.altera.com/literature/ug/ug_nios2_c2h_compiler.pdf, November. 2009.
  6. Bob Zeidman Verilog Designer's Library, Prentice Hall PTR, pp. 261-268, 1999.
  7. Douglas J. Smith HDL Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & FPGAs using VHDL or Verilog, Doone Publications, pp. 279-312, 1999.