JSTS:Journal of Semiconductor Technology and Science

  • 제15권1호
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  • Pages.131-144
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  • 2015
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Investigation of Hetero - Material - Gate in CNTFETs for Ultra Low Power Circuits

  • Wang, Wei (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Xu, Min (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Liu, Jichao (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Li, Na (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Zhang, Ting (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Jiang, Sitao (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Zhang, Lu (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Wang, Huan (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Gao, Jian (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications)
  • 투고 : 2014.08.19
  • 심사 : 2014.12.27
  • 발행 : 2015.02.28
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초록

An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero - material - gate CNTFET(HMG - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the performance parameters of circuits have been calculated and the optimum combinations of ${\Phi}_{M1}/{\Phi}_{M2}/{\Phi}_{M3}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product(PDP). We show that, compared to a traditional CNTFET - based circuit, the one based on HMG - CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG - CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.

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