Feasibility Study of Non-volatile Memory Device Structure for Nanometer MOSFET

나노미터 MOSFET비휘발성 메모리 소자 구조의 탐색

  • Jeong, Ju Young (Department of Electronic Engineering, The University of Suwon)
  • Received : 2015.06.03
  • Accepted : 2015.06.22
  • Published : 2015.06.30

Abstract

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

Keywords

References

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