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비정질 규소막의 공정조건이 HSG-Si 형성에 미치는 영향

Influence of the process conditions for the amorphous silicon on the HSG-Si formation

  • 정재영 (LG 디스플레이) ;
  • 강성준 (전남대학교 전기및반도체공학과) ;
  • 정양희 (전남대학교 전기및반도체공학과)
  • 투고 : 2015.10.01
  • 심사 : 2015.11.23
  • 발행 : 2015.11.30

초록

본 논문은 비정질 규소막 성장의 공정 조건이 저장 전극의 표면에 HSG-Si를 형성할 때 미치는 영향을 조사하였다. 그 결과 비정질 규소막의 인 농도가 $5.5{\pm}0.1E19atoms/cm^3$ 이상이면 HSG-Si가 제대로 형성되지 않는 인 농도 의존성을 나타내었다. 또한 HSG 두께가 $500{\AA}$ 이상에서는 전극과 전극을 단락시키는 비트 불량을 유발하기 때문에 비정질 규소막의 인농도는 $4.5E19atoms/cm^3$, HSG 임계 두께는 $450{\AA}$이 최적 조건임을 확인하였다.

In this paper, the processing conditions of the amorphous silicon film growth were investigated the effect in forming the HSG-Si on the surface of the storage electrode. As a result, when the amorphous silicon film phosphorus concentration is greater than $5.5{\pm}0.1E19atoms/cm^3$, HSG-Si is not formed correctly and showed the concentration dependency of HSG formation. Also, the optimum condition of the phosphorus concentration for amorphous silicon and HSG thickness are $4.5E19atoms/cm^3$ and $450{\AA}$, respectively, because of the HSG thickness over the $500{\AA}$ create to bit failure according to a short of the electrodes and the electrode.

키워드

참고문헌

  1. S. Mori, E. Sakagami, Y. Kaneko, and Y. Ohshima, "Bottom-Oxide scaling for Thin Nitride/Oxide interpoly dielectric in stacked-Gate Nonvolatile Memory Cells," IEEE Trans. on Electron Devices, vol. 39, no. 2, 1992, pp. 283-291. https://doi.org/10.1109/16.121684
  2. N. Matsuo, Y. Nakata, and S. Okada, "The oxide nitride oxide film deposition on the tunnel-structured polycrystalline silicon (polysilicon) electrodes for high-density dRAMs," J. Appl. Phys., vol. 70, no. 9, 1991, pp. 5085-5089. https://doi.org/10.1063/1.349016
  3. S. Mun, S. Kang, and Y. Joung, "A study on the DC parameter matching according to the shrink of 0.13um technology," J. of the Korea Institute of Electronic Communication Sciences, vol. 9, no. 11, 2014, pp. 1227-1232. https://doi.org/10.13067/JKIECS.2014.9.11.1227
  4. S. Mun, S. Kang, and Y. Joung, "A study on the Hot Carrier Injection Improvement of I/O Transistor," J. of the Korea Institute of Electronic Communication Sciences, vol. 7, no. 8, 2014, pp. 847-852.
  5. S. Mun, S. Kang, and Y. Joung, "A study on Flicker Noise Improvement by Decoupled Plasma Nitridation," J. of the Korea Institute of Electronic Communication Sciences, vol. 9, no. 7, 2014, pp. 747-752. https://doi.org/10.13067/JKIECS.2014.9.7.747
  6. N. Matsuo, H. Ogawa, T. Kouzaki, and S. Okada, "Nucleation and growth mechanism of hemispherical grain polycrystalline silicon," J. of Appl. Phys. Lett., vol. 60, no. 21, 1992, pp. 2607-2609. https://doi.org/10.1063/1.106923
  7. A. Sakai, T. Tatsumi, and K. Ishida, "Growth kinetics of Si hemispherical grains on clean amorphous Si surfaces," J. of Vacuum Science, vo1. 11, no. 6, 1993, pp. 2950-2953. https://doi.org/10.1116/1.578674
  8. H. Watanabe, T. Tatsumi, and S. Ohnishi, "Hemispherical grained Si formation on in-situ phosphorus doped amorphous-Si electrode for 256Mb DRAMs capacitor," IEEE. Trans. Electron Devices, vol. 42, no. 7, 1995, pp. 1247-1254. https://doi.org/10.1109/16.391206
  9. H. Watanabe, A. Sakai, T. Tatsumi, and T. Niino, "Hemispherical grain silicon for high density DRAMs," Solid State Technology, vol. 35, no. 7, 1992, pp. 29-33.
  10. H. Watanabe, T. Tatsumi, and S. Ohnishi, "A new cylindrical capacitor using hemispherical grained Si for 256Mb DRAMs," IEEE Electron Devices meeting, IEDM 92, San Francisco, USA, Dec. 1992, pp. 259-262.