Journal of Korean Institute of Industrial Engineers (대한산업공학회지)

Korean Institute of Industrial Engineers (대한산업공학회)
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Correlation Analysis on Semiconductor Process Variables Using CCA(Canonical Correlation Analysis) : Focusing on the Relationship between the Voltage Variables and Fail Bit Counts through the Wafer Process

CCA를 통한 반도체 공정 변인들의 상관성 분석 : 웨이퍼검사공정의 전압과 불량결점수와의 관계를 중심으로

  • Kim, Seung Min (School of Industrial Management Engineering, Korea University) ;
  • Baek, Jun-Geol (School of Industrial Management Engineering, Korea University)
  • 김승민 (고려대학교 산업경영공학과) ;
  • 백준걸 (고려대학교 산업경영공학과)
  • Received : 2015.02.09
  • Accepted : 2015.08.21
  • Published : 2015.12.15
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Abstract

Semiconductor manufacturing industry is a high density integration industry because it generates a vest number of data that takes about 300~400 processes that is supervised by numerous production parameters. It is asked of engineers to understand the correlation between different stages of the manufacturing process which is crucial in reducing production costs. With complex manufacturing processes, and defect processing time being the main cause. In the past, it was possible to grasp the corelation among manufacturing process stages through the engineer's domain knowledge. However, It is impossible to understand the corelation among manufacturing processes nowadays due to high density integration in current semiconductor manufacturing. in this paper we propose a canonical correlation analysis (CCA) using both wafer test voltage variables and fail bit counts variables. using the method we suggested, we can increase the semiconductor yield which is the result of the package test.

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References

  1. An, D.-W., Ko, H.-H., Baek, J.-G., and Kim, J.-Y. (2009), A Yield Prediction in the Semiconductor Manufacturing Process Using Stepwise Support Vector Machine. IE Interfaces, 22(3), 252-262.
  2. Baek, D.-H. and Nam, J.-G. (2002), Semiconductor yield improvement system using the data mining. IE Interfaces, 293-300.
  3. Byun, J.-H. and Kim, Y.-G. (1998), An EVOP Procedure Using the Relationship Between Quality Characteristics and Process Factor Conditions. IE interfaces, 1, 1-5.
  4. Chien, C. F., Wang, W. C., and Cheng, J. C. (2007), Data mining for yield enhancement in semiconductor manufacturing and an empirical study. Expert Systems with Applications, 33(1), 192-198. https://doi.org/10.1016/j.eswa.2006.04.014
  5. Hsu, S. C. and Chien, C. F. (2007), Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing. International Journal of Production Economics, 107 (1), 88-103. https://doi.org/10.1016/j.ijpe.2006.05.015
  6. Hotelling, H. (1936), Relations between two sets of variates. Biometrika, 28, 321-377. https://doi.org/10.1093/biomet/28.3-4.321
  7. Jung, S.-Y. and Sung, I.-H. (2013), Investigation of the Relationship Between Various Process Parameters and Chatter Scratch Formation in Chemical-Mechanical Polishing. Journal of the KSTLE, 57, 133-134.
  8. Kim, K.-N., Hwang, C.-G., and Lee, J.-G. (1998), DRAM technology perspective for gigabit era. Electron Devices. IEEE Transactions on, 45(3), 598-608. https://doi.org/10.1109/16.661221
  9. Kim, K.-H. and Baek, J.-G. (2014), A Prediction of Chip Quality using OPTICS (Ordering Points To Identify the Clustering Structure)-based Feature Extraction at the Cell Level. Journal of the Korean Institute of Industrial Engineering, 40(4), 404-414. https://doi.org/10.7232/JKIIE.2014.40.4.404
  10. Kubat, M., Holte, R., and Matwin, S. (1997), Learning when negative examples abound, Proceedings of the 9th European Conference on Machine Learning, ECML-97, 146-153.
  11. Lee, C.-J., Park, C.-S., Kim, J.-S., and Baek, J.-G. (2015), A Study on Improving Classification Performance for Manufacturing Process Data with Multicollinearity and Imbalanced Distribution. Journal of the Korean Institute of Industrial Engineering, 41(1), 25-33. https://doi.org/10.7232/JKIIE.2015.41.1.025
  12. Lee, Y.-J. (2002), Understanding of the Canonical correlation analysis. Seok-Jung Moonhwasa, 27-54.
  13. Ludwig, L., Sapozhnikova, E., Lunin, V., and Rosenstiel, W. (2000), Error classification and yield prediction of chips in semiconductor industry applications, Neural Computing and Applications, 9(3), 202-210. https://doi.org/10.1007/s005210070013
  14. Park, S.-R., Kim, J.-S., Park, C.-S., Park, S.-H., and Baek, J.-G. (2014), Under Sampling for Imbalanced Data using Minor Class based SVM (MCSVM) in Semiconductor Process. Journal of the Korean Institute of Industrial Engineering, 40(4), 404-414. https://doi.org/10.7232/JKIIE.2014.40.4.404
  15. Pieter, P. B. (2000), 2000 begins with a revised industry roadmap. Solid State Technology, 31-44.
  16. Quirk, M. and Serda, J. (2001), Semiconductor manufacturing technology, USA : Prentice Hall, 1, 49-50.
  17. Seok, J.-W., Kim, T.-H., and Bae, G.-S. (2012), Underwater Target Analysis Using Canonical Correlation Analysis. Journal of Korean Institute of Information and Communication, 16(9) 1878-1883. https://doi.org/10.6109/jkiice.2012.16.9.1878
  18. Sohn, S.-Y. and Lee, S.-G. (2012), Probe test yield optimization based on canonical correlation analysis between process control monitoring variables and probe bin variables. Expert Systems with Applications, 33(1) 192-198. https://doi.org/10.1016/j.eswa.2006.04.014
  19. Uzsoy, R., Lee, C. Y., and Martin-Vega, L. A. (1992), A review of production planning and scheduling models in the semiconductor industry part I : system characteristics, performance evaluation and production planning. IE transactions, 24(4), 47-60. https://doi.org/10.1080/07408179208964233