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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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A New Multi-site Test for System-on-Chip Using Multi-site Star Test Architecture

  • Han, Dongkwan (Department of Electrical and Electronics Engineering, Yonsei University) ;
  • Lee, Yong (Department of Electrical and Electronics Engineering, Yonsei University) ;
  • Kang, Sungho (Department of Electrical and Electronics Engineering, Yonsei University)
  • Received : 2013.05.13
  • Accepted : 2013.09.16
  • Published : 2014.04.01
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Abstract

As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

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