정보과학회 컴퓨팅의 실제 논문지 (KIISE Transactions on Computing Practices)

  • 제20권9호
  • /
  • Pages.483-491
  • /
  • 2014
  • /
  • 2383-6318(pISSN)
  • /
  • 2383-6326(eISSN)
한국정보과학회 (Korean Institute of Information Scientists and Engineers)
권호 표지
DOI QR코드

DOI QR Code

주메모리 접근을 고려한 CPU 주파수 조정 제한

Limiting CPU Frequency Scaling Considering Main Memory Accesses

  • 투고 : 2014.04.02
  • 심사 : 2014.06.02
  • 발행 : 2014.09.15
⟨ 이전 논문 다음 논문 ⟩

초록

현대의 컴퓨터 시스템에서는 동적 전압/주파수 조정(DVFS: Dynamic Voltage/Frequency Scaling) 기법을 이용하여 성능과 전력 소모의 균형을 이루도록 한다. DVFS 정책의 유용성은 높아진 주파수에 따른 소모 전력에 대한 성능 향상 정도에 달려있다. 특히 메모리 I/O가 많은 응용의 경우 CPU 주파수 상승에 비례하여 성능이 향상되지 않는 경우가 많다. 본 논문에서는 메모리 접근 빈도에 기반하여 CPU 주파수 조정의 상한을 결정하도록 하였다. 명령어 당 메모리 접근(최종 수준 캐시 미스) 빈도에 따라 CPU 주파수 상향으로 인한 성능 향상이 제한되는 것을 실험으로 확인하고, 성능 향상의 이득이 작아지는 CPU 주파수를 제시하도록 한다. 본 논문의 기법을 적용한 실험 결과는 메모리 접근 빈도가 높은 응용에 대하여 30% 이상의 에너지 효율 상승이 있음을 보인다.

Contemporary computer systems exploits DVFS (Dynamic Voltage/Frequency Scaling) technology for balancing performance and power consumption. The efficiency of DVFS depends on how much performance we get for larger power consumption due to elevated CPU frequency. Especially for memory-bounded applications, higher CPU frequency often does not result in higher performance. In this paper, we present an upper bound of CPU frequency scaling based on memory accesses. It is observed that the performance gain due to higher CPU frequency is limited by memory accesses (last level cache misses) per instructions by experiments. Using the results, we present the CPU frequency upper bound with little performance gain. Experimental results show that for a memory-bounded application, applying the frequency upper bound enhances the energy efficiency of the application by above 30%.

키워드

과제정보

연구 과제 주관 기관 : 인천대학교

참고문헌

  1. M. Weiser, B. Welch, A.J. Demer, and S. Shenker, "Scheduling for Reduced CPU Energy," Proceedings of the 1st USENIX Conf. on Operating Systems Design and Implementation, pp.13-23, 1994.
  2. D. Brodowski, "Linux CPUFreq Governors," [Online]. Available: https://www.kernel.org/doc /Documentation/cpu-freq/governors.txt (retrieved 2014, Mar. 25)
  3. D. Marculescu, "On the Usage of Microarchitecture-driven Dynamic Voltage Scaling," Proceedings of the Workshop on Complexity-Effective Design, 2000.
  4. Q. Wu, M. Martonosi, D.W. Clark, V.J. Reddis, D. Connors, Y. Wu, J. Lee, and D. Brooks, "A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance," MICRO 38: Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture, pp.271-282, 2005.
  5. C. Poellabauer, L. Singleton, and K. Schwan, "Feedback Based Dynamic Voltage and Frequency Scaling for Memory-bound Real-time Applications," Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, pp.234-243, 2005.
  6. K. Choi, R. Soma, and M. Pedram, "Dynamic Voltage and Frequency Scaling Based on Workload Decomposition," Proceedings of the 2004 International Symposium on Low Power Electronics and Design, pp.174-179, 2004.
  7. K. Rajamani, H. Hanson, J. Rubio, S.Ghiasi, and F. Rawson, "Application-Aware Power Management," Proceedings of the IEEE Symposium on Workload Characterization, pp.39-48, 2006.
  8. V. Venkatachalam and M. Franz, "A New Way of Estimating Compute-boundedness and Its Application to Dynamic Voltage Scaling," International Journal of Embedded Systems, vol.3, nos.1/2, pp.17-30, 2007. https://doi.org/10.1504/IJES.2007.016030
  9. M.A. Laurenzano, M. Meswani, L. Carrington, A. Snavely, M.M. Tiki, S. Poole, "Reducing Energy Usage with Memory and Computation-aware Dynamic Frequency Scaling," Proceedings of the 17th International Conference of Parallel Processing, pp.79-90, 2011.
  10. R. Miftakhutdinov, E. Ebrahimi, and Y.N. Patt, "Predicting Performance Impact of DVFS for Realistic Memory Systems," Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, pp.155-165, 2012.
  11. ARM Limited (2012, Dec. 19), "PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual," [Online]. Available: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246c/DDI0246C_l2cc_pl310_r2p0_trm.pdf (retrieved 2014, Mar. 25)
  12. http://icl.cs.utk.edu/projects/llcbench/
  13. http://web2.clarkson.edu/class/cs644/isolation/index.html
  14. M. R. Hollander and P. V. Bolotoff, "RAMspeed, a cache and memory benchmarking tool," [Online]. Available: http://alasir.com/software/ramspeed/ (retrieved 2014, Mar. 25)
  15. http://www.webkit.org/perf/sunspider/sunspider.html
  16. Samsung Electronics, "DDR3 SDRAM Specification," Rev.1.4, Nov. 2011.

피인용 문헌

  1. Design and Implementation of Low-power Neuromodulation S/W based on MSP430 vol.53, pp.7, 2016, https://doi.org/10.5573/ieie.2016.53.7.110