Korean Journal of Computational Design and Engineering (한국CDE학회논문집)

Society for Computational Design and Engineering (한국CDE학회)
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Bottleneck Detection Framework Using Simulation in a Wafer FAB

시뮬레이션을 이용한 웨이퍼 FAB 공정에서의 병목 공정 탐지 프레임워크

  • Yang, Karam (Department of Industrial Engineering, Ajou University) ;
  • Chung, Yongho (Department of Industrial Engineering, Ajou University) ;
  • Kim, Daewhan (Defense Agency for Technology and Quality) ;
  • Park, Sang Chul (Department of Industrial Engineering, Ajou University)
  • Received : 2014.05.07
  • Accepted : 2014.07.18
  • Published : 2014.09.01
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Abstract

This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

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References

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