참고문헌
- S. P. Robert : Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs, Proceedings of the IEEE, 94-6 (2006), 1214-1224 https://doi.org/10.1109/JPROC.2006.873612
- W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer and P. D. Franzon : Demystifying 3D ICs: the pros and cons of going vertical, Design & Test of Computers, IEEE, 22-6 (2005), 498-510 https://doi.org/10.1109/MDT.2005.136
- P. Garrou, C. Bower and P. Ramm : Handbook of 3D Integration: Technology and Application of 3D Integrated Circuits Volume 1 & 2, published by WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim, 2008, 22-35
- J. A. T. Norman, M. Perez, S.E. Schulz, T. Waechtler : New precursors for CVD copper metallization, Microelectron. Eng., 85-100 (2008), 2159-2163 https://doi.org/10.1016/j.mee.2008.05.036
- M. J. Wolf, T. Dretschkow, B. Wunderle, N. Jurgensen, G. Engelmann, O. Ehrmann, A. Uhlig, (...), H. Reichl : High aspect ratio TSV copper filling with different seed layers, Electronic Components and Technology Conference, (2008), 563-570
- S. J. Hong, J. H. Jung, J. P. Jung, M. Mayer, Y. N. Zhou : Sn bumping without photoresist mould and Si dice stacking for 3-D packaging, IEEE Transactions on Advanced Packaging, 33-4 (2010), 912-917 https://doi.org/10.1109/TADVP.2010.2049019
- S. C. Hong, W. G. Lee, J. K. Park, W. J. Kim, and J. P. Kim : Cu filling into TSV and non-PR Sn bumping for 3 dimension chip packaging, J. Korean Weld. Join. Soc., 29-1 (2011), 9-13 (in Korean) https://doi.org/10.5781/KWJS.2011.29.1.009
- S. H. Choa and C. G. Song : Thermo-mechanical reliability analysis of copper TSV, J. Korean Weld. Join. Soc., 29-1 (2011), 46-51 (in Korean) https://doi.org/10.5781/KWJS.2011.29.1.046
- N. Ranganathan, L. Ebin, L. Linn, L. W. Sheng Vincent, O.K. Navas, V. Kripesh and N. Balasubramanian : Integration of High Aspect Ratio Tapered Silicon Via for Through-Silicon Interconnection, Electronic Components and Technology Conference, 2008, 859-865
- H. S. Lee, K. H. Kim and S. H. Choa : Warpage and Stress Simulation of Bonding Process-Induced Deformation for 3D Package Using TSV Technology, Journal of the Korean Society of Precision Engineering 29-5 (2012), 563-571 https://doi.org/10.7736/KSPE.2012.29.5.563
- Selvanayagam, C. S., Lau, J. H., Zhang, X., Seah, S. K. W., Vaidyanathan, K. and Chai, T. C. : Nonlinear thermal stress/strain analyses of copper filled TSV and their flip-chip microbumps, Proc. Electronic Components and Technology Conference, 2008, 1073-1081
- Karmarkar, A. P. : Performance and reliability analysis of 3D-integration structures employing through silicon via (TSV), Proc. of IEEE 47th Annual International Reliability Physics Symposium, 2009, 682-687
- L. Hofmann, R. Ecke, S. E. Schulz, T. Gessner : Investigations regarding Through Silicon Via filling for 3D integration by Periodic Pulse Reverse plating with and without additives, Microelectronic Engineering, 88 (2011), 705-708 https://doi.org/10.1016/j.mee.2010.06.040
- H. L. Henry Wu and S. W. Ricky Lee : TSV Plating using Copper Methanesulfonate Electrolyte with Single Component Suppressor, Electronic System-I ntegration Technology Conference (ESTC), 2012, 1-5
- C. Wu, X. Feng, H. Cao, H. Ling, M. Li and D. Mao : The effect of different TSV electroplating levelers on the copper residual stress, Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012, 430-433
- Y. Zhua, S. Ma, X. Suna, J. Chena, M. Miao and Y. Jina : Numerical modeling and experimental veri fication of through silicon via (TSV) filling in presence of additives, Microelectronic Engineering, 117 (2014), 8-12 https://doi.org/10.1016/j.mee.2013.12.002
- N. Lin, J. Miao, P. Dixit : Void formation over limiting current density and impurity analysis of TSV fabricated by constant-current pulse-reverse modulation, Microelectronics Reliability, 53 (2013), 1943-1953 https://doi.org/10.1016/j.microrel.2013.04.003
- S. C. Hong, W. G. Lee, W. J. Kim, J. H. Kim, and J. P. Jung : Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking, Microelectron. Reliab., 51 (2011), 2228-2235 https://doi.org/10.1016/j.microrel.2011.06.031