JSTS:Journal of Semiconductor Technology and Science

  • 제14권3호
  • /
  • Pages.331-338
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  • 2014
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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A Low-Jitter Phase-Locked Loop Based on a Charge Pump Using a Current-Bypass Technique

  • Moon, Yongsam (School of Electrical and Computer Engineering, University of Seoul)
  • 투고 : 2014.01.13
  • 심사 : 2014.05.08
  • 발행 : 2014.06.30
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초록

A charge-pump circuit using a current-bypass technique, which suppresses charge sharing and reduces the sub-threshold currents, helps to decrease phase-locked loop (PLL) jitter without resorting to a feedback amplifier. The PLL shows no stability issues and no power-up problems, which may occur when a feedback amplifier is used. The PLL is implemented in 0.11-${\mu}m$ CMOS technology to achieve 0.856-ps RMS and 8.75-ps peak-to-peak jitter, which is almost independent of ambient temperature while consuming 4 mW from a 1.2-V supply.

키워드

참고문헌

  1. J.-S. Lee et al., "Charge Pump with Perfect Current Matching Characteristics in Phase-Locked Loops," Electronics Letters, vol. 36, pp. 1907-1908, Nov. 2000. https://doi.org/10.1049/el:20001358
  2. M. Terrovitis et al., "A 3.2 to 4 GHz, 0.25${\mu}m$ CMOS Frequency Synthesizer for IEEE 802.11a/b/g WLAN," IEEE ISSCC Dig. Tech. Papers, pp. 98-99, Feb. 2004.
  3. M. Johnson and E. Hudson, "A Variable Delay Line PLL for CPU-Coprocessor Synchronization," IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988. https://doi.org/10.1109/4.5947
  4. I. A. Young, J. K. Greason, and K. L. Wong, "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors," IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, Nov. 1992. https://doi.org/10.1109/4.165341

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