JSTS:Journal of Semiconductor Technology and Science

  • 제14권1호
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  • Pages.83-91
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  • 2014
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Capacitive Readout Circuit for Tri-axes Microaccelerometer with Sub-fF Offset Calibration

  • 투고 : 2013.03.05
  • 심사 : 2013.11.10
  • 발행 : 2014.02.28
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초록

This paper presents a capacitive readout circuit for tri-axes microaccelerometer with sub-fF offset calibration capability. A charge sensitive amplifier (CSA) with correlated double sampling (CDS) and digital to equivalent capacitance converter (DECC) is proposed. The DECC is implemented using 10-bit DAC, charge transfer switches, and a charge-storing capacitor. The DECC circuit can realize the equivalent capacitance of sub-fF range with a smaller area and higher accuracy than previous offset cancelling circuit using series-connected capacitor arrays. The readout circuit and MEMS sensing element are integrated in a single package. The supply voltage and the current consumption of analog blocks are 3.3 V and $230{\mu}A$, respectively. The sensitivities of tri-axes are measured to be 3.87 mg/LSB, 3.87 mg/LSB and 3.90 mg/LSB, respectively. The offset calibration which is controlled by 10-bit DECC has a resolution of 12.4 LSB per step with high linearity. The noise levels of tri-axes are $349{\mu}g$/${\sqrt}$Hz, $341{\mu}g$/${\sqrt}$Hz and $411{\mu}g$/${\sqrt}$Hz, respectively.

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참고문헌

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피인용 문헌

  1. Capacitive analog front-end circuit with dual-mode automatic parasitic cancellation loop vol.23, pp.2, 2017, https://doi.org/10.1007/s00542-017-3288-x
  2. Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors vol.15, pp.10, 2015, https://doi.org/10.3390/s151026009