An Extended Switched-inductor Quasi-Z-source Inverter

Abstract

In this paper, an extended switched-inductor quasi-Z-source inverter (ESL-qZSI) with high boost voltage inversion ability is presented, which combines the SL-qZSI with the traditional boost converter, as well as improves the switched-inductor cell. Compared with the classic qZSI topologies, the proposed topology reduces the voltage stresses of capacitors, power devices and diodes for the same input and output voltage. Furthermore, the conversion efficiency is improved. The operation principle of the proposed topology is analyzed in details, which is followed by the comparison between the three topologies. In addition, the performance of the proposed topology is verified by simulations and experiments.

1. Introduction

Z-source inverter (ZSI) [1] is widely used in low-voltage input applications such as photovoltaic, fuel cells, motor drivers et al due to its outstanding advantages compared with the traditional voltage source inverter (VSI) [2-5]. The drawbacks of the classic ZSI are significant: 1) large voltage stress across the switches and capacitors; 2) huge inrush current; 3) the input current is discontinuous; 4) there is no common ground point between dc source and inverter. Worst of all, the boost ability is too small. Several control strategies are provided to overcome these disadvantages of the classic ZSI [6-8], but they still have limits to avoid the discontinuous input current, as well as reduce the voltage stress. More importantly, the stronger boost ability is achieved, the larger shoot-through duty ratio should be used, which will result in a poor output voltage profile and low voltage-conversion ratio. Thus, the control strategies are not efficient to improve the boost ability. Another solution is to change the structure of Zsource network, which has been studied extensively [9-22].

In [9] and [10], an improved ZSI is proposed to reduce the capacitor voltage stress and inrush current startup. In [11], dc sources are directly embedded into the Z-source impedance network, which reduces the current/voltage stress and makes the input current continuous. However, they still have the same boost gain as the traditional ZSI. In [12], a novel family of extended-boost ZSIs is given, where diode-assisted or capacitor-assisted is applied to increase boost ability and the input current becomes continuous. Nevertheless, the extended-boost ZSIs have some visible shortcomings, for instance, unobvious boost effect, complicated structure and bulk size. A voltage-fed quasi-Zsource inverters (qZSI) with continuous input current, as shown in Fig. 1 (a), is proposed by F.Z. Peng et al [13-14] with lower rating and number of power devices, as well as lower current stress for dc source. Moreover, there is a common ground point between dc source and inverter, but the boost ability of the qZSI is still limited.

Trans-Z-source inverter, TZ-source inverter and Γ-Zsource inverter derived from original ZSI / qZSI are presented in [15-17], where coupled inductors are used to replace the separated ones. Thus the dc link voltage is boosted according to the changes of turn ratios or shootthrough duty ratio. However, the effect of the leak inductance is inevitable.

Switched-inductor (SL) technique is used in ZSI/qZSI topologies to achieve high boost capability, which will also lead to size saving and high power density [18-21]. Compared with the switched-inductor Z-source inverter (SL-ZSI) [18, 19], switched-inductor quasi Z-source inverter (SL-qZSI) [20, 21] derived from Fig. 1 (a) has low stress on the capacitors, inductors and diodes, as well as continuous input current. Moreover, at startup, the SLqZSIs can avoid the inrush current, which may destroy the switching devices. Another voltage-fed qZSI, shown in Fig. 1 (b), features lower capacitor voltage stress to result in more space-saving design than the qZSI shown in Fig. 1 (a). In [22], a new SL-qZSI is presented, which combines SL technique with qZSI topology shown in Fig. 1 (b) to enhance the boost ability, reduce stress on capacitors, diodes and inductors. But the input current of the dc source is discontinuous.

Fig. 1.Voltage-fed qZSI

Table 1.Comparison of passive components

To overcome the drawbacks of the new SL-qZSI [22] as well as improve the performance of inverter, an extended switched-inductor quasi-Z-source inverter (ESL-qZSI) is proposed in this paper, which combines the new SL-qZSI with classic boost circuit. In addition, an improved SL cell derived from [23] is used in the proposed topology to replace the original one. Although a few components are added, the proposed topology possesses much higher boost ability with the same shoot-through duty ratio than the other topologies to improve the output voltage profile. For the same input and output voltage, the proposed SL-qZSI achieves lower voltage stress on capacitors, diodes and power devices to increase the reliability. Furthermore, the conversion efficiency of the proposed topology is increased. Firstly, the operation principle of the ESL-qZSI is analyzed in details. Afterwards, comparisons with the similar topologies in literatures are followed. Finally, the feasibility of the proposed ESL-qZSI is validated by simulations and also a laboratory prototype based on a TMS320F28335 digital signal processor.

 

2. Circuit Analysis of Proposed Topology

Fig. 2 shows the general structure of ESL-qZSI, which consists of four inductors (L1, L2, L3, L4), four capacitors (C1, C2, C3, C4), four diodes (D1, D2, D3, D4), and one switch (S). Compared with the traditional qZSI topology shown in Fig. 1 (b), the proposed topology combines it with a typical boost circuit, and one inductor is replaced by an improved switched-inductor cell. Tab1 shows the comparison of passive components with other topologies. Compared with SL-qZSI [20], one inductor, two capacitors and one switch are added. Furthermore, the proposed topology uses only two more capacitors and one more switch, but three less diodes than the two SL-qZSI [21]. As seen, only a few components are added in ESL-qZSI.

Fig. 2.Proposed ESL-qZSI

Fig. 3.Equivalent circuit of the proposed ESL-qZSI under shoot-through state

The operating principle of the proposed topology is similar to the classic SL-qZSI shown in [20], and the operating state can also be simplified into two parts: shootthrough state and non-shoot-through state. Figs. 3 and Fig. 4 show the equivalent circuits of the ESL-qZSI under the two states, respectively.

In order to simplify the analysis, this topology is analyzed under the assumption that all devices are ideal. During the shoot-through state, as shown in Fig. 3, the diodes D3 and D4 are on, while D1 and D2 are off. L2, L3 and C4 are connected in parallel, while L1 and C2 are connected in series. The capacitors C1, C2 and C3 are discharged, while C4 is charged. All inductors store energy, and the corresponding voltages across L1, L2, L3 and L4 are VL1, VL2, VL3 and VL4, respectively. The voltages across C1, C2, C3 and C4 are VC1, VC2, VC3 and VC4, respectively. Thus, we can get

Similarly, in the non-shoot-through state, as shown in Fig. 4, the diodes D3 and D4 are off, while D1 and D2 are on. The capacitors C1, C2 and C3 are charged, while C4 is discharged. L2, L3 and C4 are connected in series. All inductors L1, L2, L3 and L4 transfer energy from dc voltage source to the load. Then the following expression can be obtained:

Fig. 4.Equivalent circuit of the proposed ESL-qZSI under non-shoot-through state

Set the interval of the shoot-through as DT, while nonshoot- through as (1-D)T. Then, we can get the voltage across the inductor L4 in a period from (1) and (2) based on volt-second balance principle:

Eq. (3) can be revised as

Because of the symmetry of L2 and L3, the voltages across L2 and L3 will be equal in a period. That is, VL2=VL3=VC4 in the shoot-through state, as well as VL2=VL3=(VC2 − VC4)/2 in the non-shoot-through state. Therefore, applying the volt-second balance principle to L1, L2 and L3 from (1) and (2) again, we can acquire

In a switching cycle, the voltage across the capacitor keeps nearly unchanged. Thus, the capacitor is able to be equivalent to a voltage source, so we can get from Fig. 3:

Substituting (4) and (6) into (5) yields:

The peak dc link voltage across the main circuit VPN can be expressed as:

Thus, the ratio between the dc link voltage VPN and the input dc voltage Vin of the proposed inverter, called the boost factor B, is defined as:

The ESL-qZSI will be able to obtain high voltageconversion ratios when shoot-through duty ratio D ≤ 1/3. Fig. 5 shows the relationship between the boost factor and shoot-through duty cycle for different topologies by using the simple boost control method. As seen, the boost ability of the proposed ESL-qZSI is significantly higher compared to that of the other three topologies shown in [13, 20] and [21] with the same shoot-through interval.

Fig. 5.Comparison of the boost ability of different topologies using simple boost control method

 

3. Comparison with Precious Topologies

Voltage stress is an important factor which will affect the performance of the qZSI, as well as determine the cost and size of the inverter [9]. Therefore, it is necessary to carry on comparisons between the different qZSI topologies under the same condition. Simple boost control, maximum boost control and maximum constant boost control are mainly three control methods used in ZSI and qZSI topologies. Compared with the simple boost control and maximum boost control, maximum constant boost control is able to achieve maximum voltage gain with constant shoot-through duty ratio, which will eliminate the lowfrequency current ripple to reduce volume and size of Zsource network [8]. Thus, for the following comparisons in this paper, maximum constant boost control is used for the analysis, as well as the simulations and experiments to verify the merits of the proposed topology.

Fig. 6.Sketch map of maximum constant boost control method

Fig. 6 shows the sketch map of maximum constant boost control for the proposed ESL-qZSI. In Fig. 6, the modulation waves Va, Vb and Vc are consist of original three phase-voltage references and a third-harmonic component with 1/6 of fundamental component. Vp and Vn are two constant voltages to determine the shoot-through duty ratio, as well as Vp, Vn are peak and minimum value of modulation waves, respectively. S1 − S6 are control signals for switching devices of the three phase bridge, while S determines the operating state of per-stage boost circuit. As we can see in Fig. 6, the switching operation is consistent with the analysis of equivalent circuits. As described in [1], the voltage gain G can be expressed as

Where is the output peak phase voltage, Vin is the input dc voltage, M is the modulation index, and B is the boost factor. As shown in [6], when we use the maximum constant boost control, the average duty cycle of the shootthrough state D is described as

Where T0 is the shoot-through time interval over a switching period T. Substituting (9) and (11) into (10) yields the voltage gain G of the proposed topology, which can be expressed as

Assuming that all inverters have the same input voltage Vin and output voltage Vo under the maximum constant boost control, that is, all inverters have the same voltage gain G. Hence, according to (11) and (12), we can get the shoot-through duty ratio D of the ESL-qZSI, which is defined by voltage gain G:

Substituting (13) into (7), we can obtain the voltage stress across the capacitor C1 of the proposed topology shown in Fig. 2, which is described as

Similarly, the capacitor voltages in the same position of the topologies mentioned in [13] and [20], can be also replaced by the voltage gain G using the same control method, which are described as VC12 and VC13, respectively

And the modulation index M2 of the SL-qZSI topology mentioned in [20] is expressed as

Where the respective coefficients can be rewritten as the following:

Fig. 7 shows the voltage stress of capacitor C1 for different topologies, where abscissa refers to the voltage gain G and ordinate stands for the ratio of capacitor voltage stress Vc1i (i=1, 2, 3) and input voltage Vin. As seen, compared with the other two topologies, the voltage stress across C1 of the ESL-qZSI is lower under the same voltage gain.

Similar to the analysis for capacitor C1, substituting (13) into (7), we can also obtain the capacitor voltage stress across C2 for the ESL-qZSI, SL-qZSI and traditional qZSI, which are described by (18):

Fig. 7.Comparison of the voltage stresses across C1 of the different topologies under maximum constant boost control method

Fig. 8.Comparison of the voltage stresses across C2 of the different topologies under maximum boost control

Fig. 8 shows the capacitor voltage stress across C2 for the three topologies. With the same voltage gain, the voltage stress across C2 of the proposed topology is the lowest, while that of the other two topologies is exactly the same.

The voltage stress across the switching devices is determined by the dc bus voltage VPN for the qZSIs. Therefore, substituting (13) into (9), the dc link voltage VPN1 of the proposed ESL-qZSI is:

The dc link voltages of the SL-qZSI and traditional qZSI can also be described as VPN2 and VPN3, respectively:

During the shoot-through state, as shown in Fig. 3, reverse voltage across the diode D1 of ESL-qZSI can be described as: VD11 = VC11 +VC21 +VC31

As seen in (2), VD11 is equal to the dc link voltage VPN1 of the proposed topology. Similarly, the reverse voltages across the diodes of the other two topologies in the same position VD12, VD13 are equal to the dc link voltages VPN2, VPN3, respectively.

Fig. 9 shows the dc link voltage comparison of the three topologies, where abscissa refers to the voltage gain G and ordinate stands for the ratio of dc bus voltage VPNi (i=1,2,3) and input voltage Vin. As shown in Fig. 9, with the same voltage gain G, the proposed ESL-qZSI has a lower voltage stress across both switching devices and diodes than those of the other two topologies.

Fig. 9.Comparison of the dc bus voltages of the different topologies under maximum constant boost control

Table 2.Capacitors and diodes with maximum voltage stress in each topology

Table 2 shows the capacitors and diodes which have maximum voltage stress in each topology. As seen, the capacitor C2 possesses the highest voltage stress in ESLqZSI and SL-qZSI, while the capacitor C1 has to take higher voltage in the traditional qZSI. From [13], we can conclude the voltage stress across C1 is higher than that across C2 in the traditional qZSI, that is, VC13>VC23. Furthermore, as shown in Fig. 8, the voltage across C2 of the proposed topology is the lowest. Thus, we can get VC13>VC22>VC21. From Table 2, we can also conclude that the diode D1 achieves maximum reverse voltage in each topology. Hence, ESL-qZSI also has lower voltage stress than that of the other two topologies. Therefore, the proposed topology is beneficial to choose lower-voltage components, which will result in space-saving and costreducing design.

 

4. Simulation Results

To verify the merits of the proposed ESL-qZSI shown in Fig. 2, the simulation results, as shown from Fig. 10 to Fig. 13, compare the performance with that of SL-qZSI and qZSI shown in [20] and [13], and Table 3 provides the list of the simulation parameters for the three topologies.

Fig. 10 shows the dc bus voltages of the three topologies when using simple boost control method, and the shootthrough duty ratio is 0.2. As seen, the dc bus voltage of the proposed topology is much higher than that of the other two topologies, which indicates that the proposed topology has stronger boost ability. As shown in Fig. 11, during the steady state, VPN is boosted to 300V when the input dc voltage Vin is 48V, the output phase voltage peak value is 100V, and VC1, VC2, VC3 and VC4 of the proposed SL-qZSI are 60V, 180V, 60V and 120V, which are the same with the theoretical analysis.

Table 3.Simulation Parameters of Three qZSIs

Fig. 10.Simulation results of the dc link voltages based on the different topologies under simple boost control method

Fig. 11.Simulation results of the proposed topology under simple boost control method

Fig. 12.Simulation results of the dc link voltages and output voltages of the different topologies under maximum constant boost control method

Fig. 12 and Fig. 13 are the simulation results of the three topologies when using maximum constant boost control to produce the same input and output voltages. Fig. 12 shows the simulation results of the three phase voltages and dc link voltages for the ESL-qZSI, SL-qZSI and traditional qZSI when M1=0.96, M2=0.79 and M3=0.68, respectively. The output phase peak voltage is 100V, while the phase resistive load is 5Ω. When the output phase voltages of the three topologies are almost the same, the dc bus voltage of the proposed topology is the smallest, which means the voltage stress across the IGBTs of the proposed topology is smaller than that of the other two topologies.

Fig. 13.Simulation results of the different topologies under maximum constant boost control method

Fig. 14.Experimental results of the proposed topology under simple boost control when D=0.2: (a) From top to bottom: input dc voltage, output phase voltage, and dc link voltage; (b) From top to bottom: input dc voltage, capacitor C1 voltage, capacitor C2 voltage, and dc link voltage.

Fig. 13 shows the capacitor voltages across C1, C2 and reverse voltage across diode D1 of the three topologies. In the steady state, the voltage stress across C1, C2 and D1 of the proposed topology are all less than those of the other two topologies. Thus, the simulation results are in good agreement with the proposed theoretical analysis

 

5. Experimental Results

Experiments for the three topologies with the same parameters shown in Table 3 are conducted to verify the properties of the proposed ESL-qZSI. Fig. 14 shows the experimental results for the proposed inverter by using simple boost control method when shoot-through duty ratio is 0.2. In Fig. 14 (a), VPN is boosted to 280V when the input voltage Vin is 48V as well as the output phase voltage peak value is 100V. In Fig. 14 (b), VC1, VC2 and VPN are boosted to 58V, 170V and 283V, respectively. The boost ability of the experimental results is smaller than the simulation value due to parasitic resistance on inductors and on-state voltage drop of diodes.

Fig. 15.Experimental results of the three topologies under maximum constant boost control method when (a) M1=0.95, (b) M2=0.773 and (c) M3=0.67.

Figs. 15 and Fig. 16 show the experimental results for the three topologies by using maximum constant boost control. To produce the same phase voltage (100 V/peak value), the modulation index for the proposed ESL-qZSI, SL-qZSI and classic qZSI is M1=0.95, M2=0.773 and M3=0.67, respectively, and the experiment uses a 100Ω/phase resistive load.

Fig. 16.Experimental results of the three topologies under maximum constant boost control when (a) M1= 0.95, (b) M2=0.773 and (c) M3=0.67.

In Fig. 15, the waveforms from top to bottom are the dc link voltage and output phase voltage Va. As seen, the dc link voltage of the propose SL-qZSI VPN1 is 200 V, which is the smallest, while the output phase peak voltages of the three topologies are all 100 V.

Fig. 17.Efficiency comparison of the three topologies by using maximum constant boost control

In Fig. 16, the waveforms from top to bottom are the voltages across C1, C2, and reverse voltage across diode D1 respectively. For the proposed ESL-qZSI, as shown in Fig. 16 (a), the voltages across C1, C2 are 33V, 110V, while the reverse voltage across D1 is 200V. For the SL-qZSI, the voltages across C1, C2 are 113V, 120V, while the reverse voltage across D1 is 240V, which is shown in Fig. 16 (b). For the classic qZSI, the voltages across C1, C2 are 170V, 120V, while the reverse voltage across D1 is 280V, which is shown in Fig. 16 (c). From the comparison, we can conclude that the voltage stress on capacitors, switching devices and diodes of the proposed ESL-qZSI are all the smallest in the three topologies. Fig. 17 shows the efficiency comparison of the three topologies when using the maximum constant boost control. Due to the smaller shoot-through time, the proposed ESL-qZSI is able to achieve higher conversion efficiency.

 

6. Conclusion

This paper has proposed an ESL-qZSI by combining traditional SL-qZSI with boost converter as well as applying an improved SL cell. Compared with the original qZSIs, the proposed ESL-qZSI has the following main characteristics: obtains high boost ability with continuous input current; offers lower voltage stress across capacitor, switching devices as well as diodes for the same input and output voltage. Furthermore, the proposed topology will be able to achieve higher conversion efficiency. The effectiveness of the analysis for the proposed ESL-qZSI is verified by simulations and experiments under both simple boost and maximum constant boost control methods. According to above, it can be concluded that the proposed ESL-qZSI is more applicable for the distributed generation applications with low voltage sources, such as fuel cells, photovoltaic and so on.