전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제51권1호
  • /
  • Pages.97-103
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  • 2014
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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1/8-Rate Phase Detector를 이용한 클록-데이터 복원회로

A Clock-Data Recovery using a 1/8-Rate Phase Detector

  • 배창현 (한양대학교 전자컴퓨터통신공학과) ;
  • 유창식 (한양대학교 전자컴퓨터통신공학과)
  • Bae, Chang-Hyun (Department of Electronics and Computer Engineering, Hanyang University) ;
  • Yoo, Changsik (Department of Electronics and Computer Engineering, Hanyang University)
  • 투고 : 2013.10.25
  • 발행 : 2014.01.25
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초록

본 논문에서는 1/8-rate 위상검출기를 이용한 클록-데이터 복원회로를 제안한다. 기존의 full-rate 또는 half-rate 위상검출기의 사용은 동일 데이터 속도에서 복원된 클록의 주파수가 상대적으로 높아야 하므로 샘플링회로와 VCO의 설계에 부담으로 작용한다. 본 논문에서는 복원된 클록의 주파수를 낮추기 위해 1/8-rate 클록을 사용할 수 있는 위상검출기를 구성하고 Linear equalizer를 위상검출기 입력에 사용하여 복원된 클록의 지터를 감소시켰다. 테스트 칩은 0.13-${\mu}m$ CMOS 공정으로 제작되었고 입력은 3-Gb/s PRBS 데이터 패턴, 동작전압은 1.2-V에서 측정되었다.

In this paper, a clock-data recovery using a 1/8-rate phase detector is proposed. The use of a conventional full or half-rate phase detector requires relatively higher frequency of a recovered clock, which is a burden on the design of a sampling circuit and a VCO. In this paper, a 1/8-rate phase detector is used to lower the frequency of the recovered clock and a linear equalizer is used as a input circuit of a phase detector to reduce the jitter of the recovered clock. A test chip fabricated in a 0.13-${\mu}m$ CMOS process is measured at 1.5-GHz for a 3-Gb/s PRBS input and 1.2-V power supply.

키워드

참고문헌

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