한국인터넷방송통신학회논문지 (The Journal of the Institute of Internet, Broadcasting and Communication)

  • 제14권6호
  • /
  • Pages.259-265
  • /
  • 2014
  • /
  • 2289-0238(pISSN)
  • /
  • 2289-0246(eISSN)
한국인터넷방송통신학회 (The Institute of Internet, Broadcasting and Communication)
권호 표지
DOI QR코드

DOI QR Code

멀티코어 프로세서의 통계적 모의실험에 관한 연구

A Study on Statistical Simulation of Multicore Processor Architectures

  • 이종복 (한성대학교 정보통신공학과)
  • Lee, Jongbok (Dept. of Information and Communications Engineering, Hansung University)
  • 투고 : 2014.11.03
  • 심사 : 2014.12.12
  • 발행 : 2014.12.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

현재 널리 이용되는 멀티코어 프로세서 구조의 설계 초기에 그 성능을 분석하기 위하여 명령어 트레이스 모의실험을 이용하는 경우, 시간과 공간을 많이 차지하기 때문에 비실용적이다. 본 논문에서는 프로화일링 기법에 기반하는 통계적 모의실험에 의하여 다양한 하드웨어 사양을 갖는 멀티코어 프로세서의 성능을 측정하는 기법에 대하여 연구하였다. 이것을 위하여 SPEC 2000 벤치마크 프로그램의 특성을 통계적 프로화일링 기법으로 모델링하고 여기서 얻은 통계적 프로화일을 바탕으로 벤치마크 트레이스를 합성하여 멀티코어 프로세서에 대한 모의실험을 수행하였다. 그 결과, 통계적 모의실험에 의하여 측정한 성능이 명령어 트레이스 모의실험에 의하여 측정한 성능에 근접한 결과를 가져왔으며 모의실험 시간을 크게 단축시켰다.

When the trace-driven simulation is used for the performance analysis of widely used multicore processors in the initial design stage, much time and disk space is necessary. In this paper, statistical simulations are performed for a high performance multicore processor with various hardware configurations. For the experiment, SPEC2000 benchmarks programs are used for profiling and synthesizing new instruction traces. As a result, the performance obtained by our statistical simulation is comparable to that of the trace-driven simulation with the benefit of tremendous reduction in the simulation time.

키워드

참고문헌

  1. Jongbok Lee, "A Study of Trace-driven Simulation for Multi-core Processor Architectures," The Journal of the Institute of Internet, Broadcasting and Communication, Vol. 12, No. 3, Jun. 2012, pp. 9-13. https://doi.org/10.7236/JIWIT.2012.12.3.9
  2. Jongbok Lee, "Performance Analysis of Multicore Processor Architectures Based On Cache Size Effects," The Journal of the Institute of Internet, Broadcasting and Communication, Vol. 12, No. 6, Dec. 2012, pp. 175-180. https://doi.org/10.7236/JIWIT.2012.12.6.175
  3. Jongbok Lee, "Performance Study of Multi-core In-Order Superscalar Processor Architectures," The Journal of the Institute of Internet, Broadcasting and Communication, Vol. 12, No. 5, Oct. 2012, pp. 123-128.
  4. Jongbok Lee, "A Performance Study of Embedded Multicore Processor Architectures," The Journal of the Institute of Internet, Broadcasting and Communication, Vol. 13, No. 1, Feb. 2013, pp. 163-169. https://doi.org/10.7236/JIIBC.2013.13.1.163
  5. Jongbok Lee, "Performance Study of Multicore Digital Signal Processor Architectures," The Journal of the Institute of Internet, Broadcasting and Communication, Vol. 13, No. 14, Aug. 2013, pp. 171-177. https://doi.org/10.7236/JIIBC.2013.13.4.171
  6. Jongbok Lee, "The Processor Performance Model Using Statistical Simulation," The Jounral of the Korean Institute of Information Scientists and Engineers, Vol. 33, No. 5-6, Jun. 2006, pp. 297-305.
  7. R. Carl and J. E.Smith, "Modeling Superscalar Processors via Statistical Simulation," Workshop on Performance Analysis and Its Impact on Design, Jun. 1998.
  8. T. Ungerer, B. Robic, and J. Silk, "Multithreaded Processors," The Computer Journal, Vol. 45, No. 3, 2002
  9. G. S. Sohi, S. E. Breach, and T. N. Vijaykumar, "Multiscalar Processors," Proceedings of the 22nd annual international symposium on Computer architecture, pp. 414-425, May 1995.
  10. T-Y. Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," in Proceedings of the 19th International Symposium on Computer Architecture, pp.124-134, May. 1992.
  11. A. Rico, A. Duran. F. Cabarcas, Y. Etsion, A. Ramirex, and M. Valero, "Trace-driven Simulation of Multithreaded Applications," ISPASS, 2011.
  12. T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002. https://doi.org/10.1109/2.982917