참고문헌
- J. H. Lau, "Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration", Advanced Packaging Materials (APM), Xiamen, 462, IEEE (2011).
- P. Garrou, C. Bower and P. Ramm, "Handbook of 3D integration, Technology and Application of 3D Integrated Circuits", Volume 1, pp.22-35, John Wiley & Sons., (2008).
- S. P. Robert, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs", Proceeding of the IEEE, 94(6), 1214 (2006). https://doi.org/10.1109/JPROC.2006.873612
- J. H. Jun, I. R. Kim, M. Mayer, Y. N. Zhou, S. B. Jung and J. P. Jung, "A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging", Materials Transactions., 51(10), 1887 (2010). https://doi.org/10.2320/matertrans.M2009314
- I. H. Jeong, D. H. Jung, K. S. Shin, D. S. Shin and J. P. Jung, "Electrical Characteristics and Thermal Shock Properties of Cu-Filled TSV Prepared by Laser Drilling", Electrical Materials Letters, 9(4), 389 (2013). https://doi.org/10.1007/s13391-013-0006-4
- K. Y. K. Tsui, S. K. Yau, V. C. K. Leung, P. Sun and D. X. Q. Shi, "Parametric Study of Electroplating-based Via-filling Process for TSV Applications", International Conference on Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), Beijing, 23, IEEE (2009).
- L. Hofmann, R. Ecke, S. E. Schulz, T. Gessner, "Investigations regarding Through Silicon Via filling for 3D integration by Periodic Pulse Reverse Plating with and without additives", Microelectronic Engineering, 88(5), 705 (2011). https://doi.org/10.1016/j.mee.2010.06.040
- J. A. T. Norman, M. Perez, S. E. Schulz, T. Waechtler, "New precursors for CVD copper metallization", Microelectronic Engineering, 85(10), 2159 (2008). https://doi.org/10.1016/j.mee.2008.05.036
- Q. Li, H. Ling, H. Cao, Z. Bian, M. Li and D. Mao, "Through silicon via Filling by Copper Electroplating in Acidic Cupric Methanesulfonate Bath", International Conference on Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), Beijing, 68, IEEE (2009).
- S. C. Hong, W. J. Kim and J. P. Jung, "High-Speed Cu filling into TSV and Non-PR Bumping for 3D chip Packaging", J. Microelectron. Packag. Soc., 18(4), 49 (2011).
- S. C. Hong, W. G. Lee, W. J. Kim, J. H. Kim and J. P. Jung, "Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking", Microlectronics Reliability, 51(12), 2228 (2011). https://doi.org/10.1016/j.microrel.2011.06.031
- E. H. Choi, Y. S. Lee and S. K. Rha, "Effects of current Density and Organic Additives on Via Copper Electroplating for 3D Packaging", Kor. J. Mater Res., 22(7), 374 (2012). https://doi.org/10.3740/MRSK.2012.22.7.374
- S. C. Hong, S. Kumar, D. H. Jung, W. J. Kim and J. P. Jung, "High Speed Cu-Ni Filling into TSV for 3-Dimensional Si Chip Stacking", Met. Mater. Int., 19(1), 123 (2013). https://doi.org/10.1007/s12540-013-1020-7
- J. H. Lee, Y. S. Koo, K. T. Kim and M. W. Jung, "The Effects of Levelers on Electrodeposition of Copper in TSV Fillig", J. Microelectron. Packag. Soc., 19(2), 55 (2012). https://doi.org/10.6117/kmeps.2012.19.2.055
- E. S. Kim, M. J. Lee, S. D. Kim and S. E. K. Kim, "Ti/Cu CMP process for wafer level 3D integration", J. Microelectron. Packag. Soc., 19(3), 37 (2012). https://doi.org/10.6117/kmeps.2012.19.3.037
피인용 문헌
- Effects of Leveler Concentration in High Aspect Ratio Via Filling in 3D SiP vol.58, pp.2, 2017, https://doi.org/10.2320/matertrans.MA201607
- Three-Dimesnional Semicondoctor Stacking using TSV(Through-Si-Via) Technology vol.39, pp.3, 2014, https://doi.org/10.5781/jwj.2021.39.3.8
- A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process vol.11, pp.10, 2021, https://doi.org/10.3390/met11101664