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직렬 RLC 입력 정합 및 저항 궤환 회로를 이용한 6.2~9.7 GHz 광대역 저잡음 증폭기 설계

6.2~9.7 GHz Wideband Low-Noise Amplifier Using Series RLC Input Matching and Resistive Feedback

  • 박지안 (한국항공대학교 항공전자 및 정보통신공학부) ;
  • 조춘식 (한국항공대학교 항공전자 및 정보통신공학부)
  • Park, Ji An (School of Electronics, Telecommunication and Computer Engineering, Korea Aerospace University) ;
  • Cho, Choon Sik (School of Electronics, Telecommunication and Computer Engineering, Korea Aerospace University)
  • 투고 : 2013.09.02
  • 심사 : 2013.11.11
  • 발행 : 2013.11.30

초록

본 논문은 직렬 RLC 정합과 저항 궤환 회로를 이용하여 설계한 중심 주파수 8 GHz를 갖는 저잡음 증폭기를 제안한다. 제안하는 LNA는 입력 정합에 Degenerate inductor를 사용하여 $S_{21}$이 넓은 대역폭을 지니고 있고, 병렬로 구성된 회로를 직렬 공진 회로로 변환함으로써 입력 정합 회로를 등가회로로 축약하여 해석을 하였다. 저항 궤환 회로와 입력 RLC 정합이 모두 사용되어 제안하는 LNA는 최대 8.5 dB의 $S_{21}$(-3 dB 대역폭은 약 3.5 GHz), 잡음 지수로 5.9 dB, IIP3로는 1.6 dBm 값을 가지며, 1.2 V에서 7 mA를 소모한다.

A low-noise amplifier(LNA) using series RLC matching network and resistive feedback at 8 GHz is presented. Inductive degeneration is used for the input matching with which the proposed LNA shows quite a wide bandwidth in terms of $S_{21}$. An equivalent circuit model is deduced for input matching by conversion from parallel circuit to series resonant circuit. By exploiting the resistive feedback and series RLC input matching, fully integrated LNA achieves maximum $S_{21}$ of 8.5 dB(peak to -3 dB bandwidth is about 3.5 GHz) noise figure of 5.9 dB, and IIP3 of 1.6 dBm while consuming 7 mA from 1.2 V supply.

키워드

참고문헌

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