한국산업정보학회논문지 (Journal of Korea Society of Industrial Information Systems)

한국산업정보학회 (Korea Society of Industrial Information Systems)
권호 표지
DOI QR코드

DOI QR Code

기준 클럭 발생을 위한 저 젼력, 저 잡음 DLL기반 주파수 체배기

A Low-power, Low-noise DLL-based Frequency Multiplier for Reference Clock Generator

  • 김형필 (강원대학교 전기전자공학전공) ;
  • 황인철 (강원대학교 전기전자공학전공)
  • 투고 : 2013.08.26
  • 심사 : 2013.10.04
  • 발행 : 2013.10.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문은 DLL 기술을 사용하여서 낮은 위상잡음을 갖는 주파수 체배기를 설계 하였다. VCDL은 공통모드 잡음을 줄이기 위해서 차동구조를 이용하여 설계 되었다. 이번 설계는 65nm, 1.2V TSMC CMOS 공정을 이용 하였고, 동작 주파수 범위는 10MHz에서 24MHz로 측정되었다. TCXO를 기준 주파수로 사용하여 위상잡음을 측정하였을 때 38.4MHz의 출력에서 1MHz offset 기준으로 -125dBc/Hz가 측정되었다. 총 면적은 $0.032mm^2$을 사용하였고, 출력 버퍼를 포함하여 총 1.8mA의 전류를 칩에서 소비하였다.

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

키워드

참고문헌

  1. Kyungho Ryu; Dong-Hoon Jung; Seong-Ook Jung, "A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator,"IEEE Transactions on Circuits and Systems I Regular Papers Volume. 59 PP. 1860 - 1870, Sept. 2012. https://doi.org/10.1109/TCSI.2011.2180453
  2. Hwang. S, Kim, K.-M. ; Kim. K, Kim. C., "A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor,"IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Issue: 99 ,PP.1 - 5 , Apr 2012
  3. Seung-Jun Bae; Hyung-Joon Chi;Park, H.-J., "A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme," IEEE Journal of Solid-State Circuits , PP.1119 - 1129, May 2005
  4. Ng, H.J.; Stuhlberger, R.; Maurer, L.; Sailer, T.; Stelzer, A. "Low Phase Noise 77-GHz Fractional-N PLL with DLL-based Reference Frequency Multiplier for FMCW Radars," European Microwave Integrated Circuits Conference (EuMIC) PP.196 - 199 , 2011
  5. Pu Xiao; Abraham, J.; Thomsen, A.; Nagaraj, K. "A novel fractional-N PLL based on a simple reference multiplier," International Midwest Symposium on Circuits and Systems (MWSCAS), PP.1-4 ,2011
  6. Woojae Lee; SeongHwan Cho ,"A 2.4-GHz Reference Doubled Fractional-N PLL with Dual Phase Detector in 0.13-${\mu}m$ CMOS," International Symposium on Circuits and Systems (ISCAS), PP. 1328 - 1331, 2010
  7. Sunghwa Ok; Kyunghoon Chung ,"An Antiharmo nic, Programmable, DLL-Based Frequency Mult iplier for Dynamic Frequency Scaling," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, PP. 1130 - 1134 , 2010
  8. Chulwoo Kim; In-Chul Hwang; Sung-Mo Kang, "A low-power small-area ${\pm}7.28$-ps -jitter 1-GHz DLL-based clock generator," IEEE Journal of Solid-State Circuits, PP. 1414-1420 , 2002