JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Monte Carlo Simulation Study: the effects of double-patterning versus single-patterning on the line-edge-roughness (LER) in FDSOI Tri-gate MOSFETs

  • Park, In Jun (School of Electrical and Computer Engineering, University of Seoul) ;
  • Shin, Changhwan (School of Electrical and Computer Engineering, University of Seoul)
  • Received : 2013.03.26
  • Accepted : 2013.06.25
  • Published : 2013.10.31
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Abstract

A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).

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References

  1. X. Wang, G. Roy, O. Saxod, A. Bajolet, A. Juje, and A. Asenov, "Simulation study of dominant statistical variability sources in 32-nm high-k/metal gate CMOS," IEEE Electron. Dev, Lett., Vol. 33, No 5, pp. 643-645, May 2012. https://doi.org/10.1109/LED.2012.2188268
  2. C. Auth, et al, "A 22nm high performance and lowpower CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors," 2012 Symposium on VLSI Technology. Digest of Technical Papers, 2012, pp. 131-132.
  3. A. Khakifirooz, et al, "Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS," 2012 Symposium on VLSI Technology. Digest of Technical Papers, 2012, pp. 117-118.
  4. T. Zhao, Characterization of amorphous and crystalline rough surface: principles and applications, Academic Press, 2010.
  5. K. Cheng, et al, "Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain," 2009 Symposium on VLSI Technology. Digest of Technical Papers, 2009, pp. 212-213.
  6. Int'l Technology Roadmap for Semiconductors, 2011 Ed.
  7. X. Sun and T.-J. K. Liu, "Spacer gate lithography for reduced variability due to line edge roughness," IEEE Trans. Semiconductor Manufacturing, Vol.23, No.2, pp.311-315, May, 2010. https://doi.org/10.1109/TSM.2010.2046050
  8. Sentaurus User's Manual, v. 2010.12 (Synopsys, Inc.).
  9. H. Nam and C. Shin, "Study of high-k/metal-gate work-function variation using Rayleigh distribution," IEEE Electron Device Lett., Vol. 34, No. 4, pp. 532-534, April 2013. https://doi.org/10.1109/LED.2013.2247376
  10. C. Shin and I. J. Park, "Impact of using doublepatterning versus single-patterning on threshold voltage (VTH) variation in quasi-planar tri-gate bulk MOSFETs," IEEE Electron Device Lett., Vol 34, No. 5, pp. 578-580, May 2013. https://doi.org/10.1109/LED.2013.2249653
  11. H. F. Dadgour, et al, "Grain-orientation induced work function variation in nanoscale metal-gate transistors-part II: implications for process, device, and circuit design," IEEE Trans. Electron Devices, Vol.57, No.10, pp.2515-2525, October, 2010. https://doi.org/10.1109/TED.2010.2063270
  12. A. Asenov, "Simultion of statistical variability in nano MOSFETs," 2007 Symposium on VLSI Technology. Digest of Technical Papers, 2007, pp. 86-87.

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