Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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The noise impacts of the open bit line and noise improvement technique for DRAM

DRAM에서 open bit line의 데이터 패턴에 따른 노이즈(noise) 영향 및 개선기법

  • Received : 2013.08.21
  • Accepted : 2013.09.02
  • Published : 2013.09.30
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Abstract

The open bit line is vulnerable to noise compared to the folded bit line when read/write for the DRAM. According to the increasing DRAM densities, the core circuit operating conditions is exacerbated by the noise when it comes to the open bit line 6F2(F : Feature Size) structure. In this paper, the interference effects were analyzed by the data patterns between the bit line by experiments. It was beyond the scope of existing research. 68nm Tech. 1Gb DDR2, Advan Tester used in the experiments. The noise effects appears the degrade of internal operation margin of DRAM. This paper investigates sense amplifier power line splits by experiments. The noise can be improved by 0.2ns(1.3%)~1.9ns(12.7%), when the sense amplifier power lines split. It was simulated by 68nm Technology 1Gb DDR2 modeling.

DRAM 에서 folded bit line 대비 open bit line은 데이터 read나 write 동작시 노이즈(noise)에 취약하다. 6F2(F: Feature Size) 구조의 open bit line에서 DRAM 집적도 증가에 따라 코어(core) 회로부 동작 조건은 노이즈로부터 더욱 악화된다. 본 논문에서는 비트라인(bit line) 간 데이터 패턴의 상호 간섭 영향을 분석하여, 기존의 연구에서는 다루지 않았던 open bit line 방식에서 데이터 패턴 상호 간섭의 취약성을 실험적 방법으로 확인하였으며, 68nm Tech. 1Gb DDR2에서 Advan Test장비를 사용하여 실험하였다. 또한 open bit line 설계 방식에서 노이즈 영향이 DRAM 동작 파라미터(parameter) 특성 열화로 나타나는데, 이를 개선 할 수 있는 방법을 센스앰프 전원분리 실험으로 고찰하였다. 센스앰프 전원분리시 0.2ns(1.3%)~1.9ns(12.7%) 이상 개선될 수 있음을 68nm Tech. 1Gb DDR2 modeling으로 시뮬레이션 하였다.

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References

  1. D. Graham-Smith, "IDF: DDR3 won't catch up with DDR2 during 2009," in PC Pro, Aug. 2008.
  2. Busch, B. et al., "A 78nm 6F2 DRAM technology for multigigabit densities." VLSI Technology, Digest of Technical Papers. pp.28-29, June 2004.
  3. Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger, "Architecting phase change memory as a scalable dram alternative." ISCA '09 Proc. of the 36th international symposium on Computer architecture. pp.2-13, 2009.
  4. Hoon Jeong, et al., "55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure." Electron Devices Meeting, 2008. IEDM. pp.1-4, Dec. 2008.
  5. Zaid Al-Ars, et al, "Effects of Bit Line Coupling on the Faulty Behavior of DRAMs" Proceedings of the 22nd IEEE VLSI Test Symposium, pp. 117-122, Apri,. 2004.
  6. Kibong Koo, et al., "A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with Bank Group and x4 Half-Page Architecture" IEEE International Solid State Circuits Conference, pp.40-41, Feb. 2012.
  7. Kyomin Sohn, et al., "A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme" IEEE Journal of Solid State Circuits, Vol.48, pp. 168-177, Jan. 2013. https://doi.org/10.1109/JSSC.2012.2213512
  8. Tomonori Sekiguchi, et al., "A Low-Impedance Open-Bitline Array for Multigigabit DRAM" IEEE J. Solid-State Circuits, Vol.37, pp.487-498, Apr. 2002. https://doi.org/10.1109/4.991387
  9. Y. Nakagome et al, "The impact of data-line interference noise on DRAM scaling," IEEE J. Solid-State Circuits, Vol.23, pp.1120-1127, Oct. 1988. https://doi.org/10.1109/4.5933