전기학회논문지 (The Transactions of The Korean Institute of Electrical Engineers)

  • 제62권9호
  • /
  • Pages.1255-1259
  • /
  • 2013
  • /
  • 1975-8359(pISSN)
  • /
  • 2287-4364(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지
DOI QR코드

DOI QR Code

Spherical 구조를 갖는 고전압용 Analog CMOS의 Drain 역방향 항복전압의 계산 방법

The Calculation Method of the Breakdown Voltage for the Drain Region with the Spherical Structure in High Voltage Analog CMOS

  • Lee, Un Gu (Dept. of Information and Communication, Bucheon University)
  • Received : 2013.04.04
  • Accepted : 2013.08.13
  • Published : 2013.09.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

Abstract

A calculation method of the breakdown voltage for the Drain region with the spherical structure in high voltage analog CMOS is proposed. The Drain depletion region is divided into many sub-regions and the doping concentration of each sub-region is assumed to be constant. The field in each sub-region is calculated by the integration of the net charge and the breakdown voltage is calculated using the ionization integral method. The breakdown voltage calculated using the proposed method shows the maximum relative error of 3.3% compared with the result of the 2-dimensional device simulation using BANDIS.

Keywords

References

  1. R.S.Muller, T.I.Kamins, Device Electronics for Integrated Circuits, John Wiley & Sons, New York, pp. 32-33 2003.
  2. P. Antognetti, Power Integrated Circuits: Physics, Design, and Applications, McGraw-Hill, Italy, pp. 2.44, 1986.
  3. S.C.Sun, J.D.Plummer, "Modeling of the On-Resistance of LDMOS, VDMOS, and VMOS Power Transistor", IEEE Trans. on Electron Device, Vol. ED-27, No. 2, pp. 356-367, Feb. 1980.
  4. H.Ballan, M.Declercq, High Vlotage Device and Circuits in Standard CMOS Technologies, Kluwer Academics Pub., Netherlands, pp.6, 1999.
  5. B.Murari, F.Bertotti, G.A.Vignola, Smart Power ICs Technologies and Applications, Springer, New York, pp. 53, 1996.
  6. B. J. Baliga, Power Semiconductor Devices, PWS Pub. comp. Boston, pp. 82-102, 1996.
  7. Antonio G.M, Strollo and E. Napoli, "Optimal ON-Resistance Versus Breakdown Voltage Tradeoff in Superjunction Power Devices: A Novel Analytic Model", IEEE Trans. on Electron Device, Vol. 48, No. 9, pp. 2161-251, Sep. 2001. https://doi.org/10.1109/16.944211
  8. UnGu Lee, "The Calculation Method of the Breakdown Voltage for the Drain Region with the Cylindrical Structure in LDMOS ", Trans. KIEE. Vol. 61, No. 12, pp.1872-1876, Dev. 2012. https://doi.org/10.5370/KIEE.2012.61.12.1872
  9. UnGu Lee, A Study on the Integrated BJT Process Development for CDP Motor Drive IC Using BANDIS and MODIS Program, Inha University, 2003.