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Efficient Loop Accelerator for Motion Estimation Specific Instruction-set Processor

움직임 추정 전용 프로세서를 위한 효율적인 루프 가속기

  • Ha, Jae Myung (Department of Electrical and Computer Engineering, Ajou University) ;
  • Jung, Ho Sun (Department of Electrical and Computer Engineering, Ajou University) ;
  • Sunwoo, Myung Hoon (Department of Electrical and Computer Engineering, Ajou University)
  • Received : 2013.04.18
  • Published : 2013.07.25

Abstract

This paper proposes an efficient loop accelerator for a motion estimation specific instruction-set processor. ME algorithms in nature contain complex and multiple loop operations. To support efficient hardware (HW) loop operations, this paper introduces four loop instructions and their specific HW architecture. The simulation results show that the proposed loop accelerator can reduce about 29% average instruction cycles for ME early-termination schemes compared with typical implementation having a combination of compare and conditional jump instructions. The proposed loop accelerator of the motion estimation specific instruction-set processor can significantly reduce the number of program memory accesses and greatly save power consumption. Hence, it can be quite suitable for low power and flexible ME implementation.

본 논문은 움직임 추정 전용 프로세서를 위한 효율적인 루프 가속기를 제안한다. 실제로 움직임 추정 알고리즘은 복잡하고 다양한 순환 명령어들을 포함하고 있다. 본 논문에서는 효율적인 하드웨어 루프 명령어들을 지원하기 위해서, 네 개의 루프 명령어와 그에 따른 하드웨어 구조를 소개한다. 검증 결과 제안된 루프 가속기가 early-termination을 이용한 움직임 추정 시 비교명령어와 조건부 점프명령어를 갖고 있는 전형적인 구현 방법과 비교했을 때 평균 명령어 사이클 수를 약 29% 줄일 수 있다는 것을 보여준다. 제안된 움직임 추정 전용 프로세서 루프 가속기는 프로그램 메모리의 접근 빈도를 상당히 줄일 수 있고, 전력 소모를 많이 절약할 수 있다. 따라서, 제안된 루프 가속기는 전력 소모가 적고, 유연한 움직임 추정에 적합하다.

Keywords

References

  1. Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, ITU-T Rec. H.264 and ISO/IEC 14496-10 AVC, Joint Video Team (JVT) of ITU-T VCEG and ISO/IEC MPEG, Document JVT-G050, May 2003.
  2. T. Wiegand, W. J. Han, B. Bross, J. R. Ohm, and G. J. Sullivan, "WD1: Working Draft 1 of High-Efficiency Video Coding," ITU-T SG16/WP3 Doc. JCTVC-C403, Guangzhou, China, Oct. 2010.
  3. Y. J. Wang, C. C. Cheng, and T. S. Chang, "A fast fractional pel motion estimation algorithm for H.264/MPEG-4 AVC," in Proc. IEEE International Symposium on Circuits and Systems, May 2006, pp. 3974-3977.
  4. S. D. Kim and M. H. Sunwoo, "ASIP approach for implementation of H.264/AVC, " Journal of Signal Processing Systems, vol. 50, no. 1, pp.53-67, Jan. 2008. https://doi.org/10.1007/s11265-007-0109-y
  5. V. R. Dodani, N. Kumar, U. Nanda, and K. Mahapatra, "Optimization of an application specific instruction set processor using application description language," in Proc. IEEE Int. Conference on Industrial and Information Systems (ICIIS), July 2010, pp. 325-328.
  6. S. Momcilovic, N. Roma, and L. Sousa, "An ASIP approach for adaptive motion estimation on AVC," in Proc. IEEE 3rd Conf. on Ph.D. Research in Microelectronics and Electronics, July 2007, pp. 165-168.
  7. J. L. Nunez-Yanez, E. Hung, and V. A. Chouliaras, "A configurable and programmable motion estimation processor for the H.264 video codec," in Proc. International Conference on Field Programmable Logic and Applications, Sept. 2008, pp. 149-154.
  8. H. Peters, R. Sethuraman, A. Beric, P. Meuwissen, S. Balakrishnan, C. A. A. Pinto, W. Kruijtzer, F. Ernst, G. Alkadi, J. van Meerbergen, and G. de Haan, "Application specific instruction-set processor template for motion estimation in video applications, " IEEE Trans. on Circuits and Systems for Video Technology, vol. 15, issue 4, pp. 508-527, April 2005. https://doi.org/10.1109/TCSVT.2005.844462
  9. H. K. Eun, S. J. Hwang, M. H. Sunwoo, Y. H. Kim, and H. S. Kim, "Integer-pel Motion Estimation Specific Instructions and their Hardware Architecture for ASIP, " in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2011, pp.953-956.
  10. N. Kavvadias and S. Nikolaidis, "Elimination of overhead operations in complex loop structures for embedded microprocessors, " IEEE Trans. on Computers, vol. 57, no. 2, pp. 200-214, Feb. 2008. https://doi.org/10.1109/TC.2007.70790
  11. C. T. Wu, A. C. Hsieh, and T. T. Hwang, "Instruction buffering for nested loops in low-power design," IEEE Trans. on VLSI Systems, vol. 14, no. 7, pp. 780-784, July 2006. https://doi.org/10.1109/TVLSI.2006.878348
  12. X. Xu and Y. He, "Improvements on fast motion estimation strategy for H.264/AVC, " IEEE Trans. on Circuits and Systems for Video Technology, vol. 18, issue 3, pp. 285-293, March 2008 https://doi.org/10.1109/TCSVT.2008.918122
  13. T. Y. Kuo and H. J. Lu, "Efficient Reference Frame Selector for H.264," IEEE Trans. On Circuits and Systems for Video Technology, vol. 18, pp. 400-405, March, 2008. https://doi.org/10.1109/TCSVT.2008.918111
  14. L. Shen, Z. Liu, Z. Zhang, and G. Wang, "An adaptive and fast multiframe selection algorithm for H.264 video coding," IEEE Signal Processing Letters, vol. 14, no. 11, pp. 836-839, Nov. 2007. https://doi.org/10.1109/LSP.2007.898343
  15. L. Tao, Y. Su-ying, S. Zai-feng, and G. Peng, "An improved three-step search algorithm with zero detection and vector filter for motion estimation," in Proc. IEEE International Conference on Computer Science and Software Engineering, Vol 2, pp. 976-970, Dec. 2008.
  16. Lai-Man Po, Wing-Ching Ma, "A novel four-step search algorithm for fast block motion estimation," IEEE Trans. On Circuits and Systems for Video Technology, vol. 6, pp. 313-317, Jun. 1996. https://doi.org/10.1109/76.499840
  17. Synopsys Processor Designer Available: www.synopsys.com/Systems/BlockDesign/process orDev/Pages/default.aspx
  18. O. Ndili and T. Ogunfunmi, "Hardware-oriented modified diamond search for motion estimation in H.264/AVC, " in Proc. IEEE International Conference on Image Processing (ICIP), Sept. 2010, pp. 749-752.