전기전자학회논문지 (Journal of IKEEE)

  • 제17권2호
  • /
  • Pages.202-207
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  • 2013
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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객체인식을 위한 FAST와 BRIEF 알고리즘 기반 FPGA 설계

FPGA based Implementation of FAST and BRIEF algorithm for Object Recognition

  • Heo, Hoon (Dept. of Computer Enginerring, Seokyeong University) ;
  • Lee, Kwang-Yeob (Dept. of Computer Enginerring, Seokyeong University)
  • 투고 : 2013.06.21
  • 심사 : 2013.06.27
  • 발행 : 2013.06.30
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초록

본 논문은 기존의 FAST와 BRIEF 알고리즘을 Zynq-7000 Soc Platform에서 하드웨어로 구현했다. 대표적으로 SIFT 나 SURF 알고리즘을 사용하여 특징점 기반 하드웨어 가속기로 구현 하지만, 하드웨어 비용과 내부 메모리가 많이 필요하다. 제안하는 FAST & BRIEF 가속기는 기존의 SIFT 나 SURF 가속기 보다 내부 메모리 사용량을 약 57%, 하드웨어 비용을 약 70% 정도 감소하고, 수행 시간은 Clock 당 0.17 Pixel를 처리한다.

This paper implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per Clock.

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참고문헌

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