한국통신학회논문지 (The Journal of Korean Institute of Communications and Information Sciences)

  • 제38A권4호
  • /
  • Pages.303-309
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  • 2013
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  • 1226-4717(pISSN)
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  • 2287-3880(eISSN)
한국통신학회 (The Korean Institute of Commucations and Information Sciences)
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비교기 기반 입력 전압범위 감지 회로를 이용한 6비트 500MS/s CMOS A/D 변환기 설계

Design of a 6-bit 500MS/s CMOS A/D Converter with Comparator-Based Input Voltage Range Detection Circuit

  • 시대 (인하대학교 전자공학과) ;
  • 이상민 (인하대학교 전자공학과) ;
  • 윤광섭 (인하대학교 전자공학과)
  • 투고 : 2013.02.01
  • 심사 : 2013.04.03
  • 발행 : 2013.04.30
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초록

입력 전압 범위 감지 회로를 이용해서 저전력 6비트 플래시 500Ms/s ADC를 설계하였다. 입력 전압 범위 감지 회로는 변환기내 모든 비교기들 중에서 25%만 동작시키고, 나머지 75%는 동작시키지 않는 방법을 채택하므로 저전력 동작을 가능하게 설계 및 제작하였다. 설계된 회로는 0.13um CMOS 공정기술을 이용해서 제작하였고, 1.2V 전원전압에서 68.8mW 전력소모, 4.9 유효 비트수, 4.75pJ/step의 평가지수가 측정되었다.

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

키워드

참고문헌

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