Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Analysis of Process and Layout Dependent Analog Performance of FinFET Structures using 3D Device Simulator

3D Device simulator를 사용한 공정과 Layout에 따른 FinFET 아날로그 특성 연구

  • Noh, SeokSoon (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kwon, KeeWon (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
  • 노석순 (성균관대학교 정보통신대학) ;
  • 권기원 (성균관대학교 정보통신대학) ;
  • 김소영 (성균관대학교 정보통신대학)
  • Received : 2012.11.30
  • Published : 2013.04.25
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Abstract

In this paper, the analog performance of FinFET structure was estimated by extracting the DC/AC characteristics of the 22 nm process FinFET structures with different layout considering spacer and SEG using 3D device simulator, Sentaurus. Based on the analysis results, layout methods to enhance the analog performance of multi-fin FinFET structures are proposed. By adding the spacer and SEG structures, the drive current of 1-fin FinFET increases. However, the unity gain frequency, $f_T$, reduces by 19.4 % due to the increase in the total capacitance caused by the added spacer. If the process element is not included in multi-fin FinFET, replacing 1-finger with 2-finger structure brings approximately 10 % of analog performance improvement. Considering the process factors, we propose methods to maximize the analog performance by optimizing the interconnect and gate structures.

본 논문에서는 3차원 소자 시뮬레이터인 Sentaurus를 사용하여, spacer 및 selective epitaxial growth (SEG) 구조 등 공정적 요소를 고려한 22 nm 급 FinFET 구조에서 레이아웃에 따른 DC 및 AC 특성을 추출하여 아날로그 성능을 평가하고 개선방법을 제안한다. Fin이 1개인 FinFET에서 spacer 및 SEG 구조를 고려할 경우 구동전류는 증가하지만 아날로그 성능지표인 unity gain frequency는 total gate capacitance가 dominant하게 영향을 주기 때문에 동작 전압 영역에서 약 19.4 % 저하되는 것을 알 수 있었다. 구동전류가 큰 소자인 multi-fin FinFET에서 공정적 요소를 고려하지 않을 경우, 1-finger 구조를 2-finger로 바꾸면 아날로그 성능이 약 10 % 정도 개선되는 것으로 보이나, 공정적 요소를 고려 할 경우 multi-finger 구조의 게이트 연결방식을 최적화 및 gate 구조를 최적화 해야만 이상적인 아날로그 성능을 얻을 수 있다.

Keywords

References

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