마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제20권4호
  • /
  • Pages.69-74
  • /
  • 2013
  • /
  • 1226-9360(pISSN)
  • /
  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
권호 표지
DOI QR코드

DOI QR Code

Analyzing the Impact of Supply Noise on Jitter in GBPS Serial Links on a Merged I/O-Core Power Delivery Network

  • Tan, Fern-Nee (Malaysia Design Center, Intel Microelectronics) ;
  • Lee, Sheng Chyan (Department of Electronic and Green Technology, Tunku Abdul Rahman University)
  • 투고 : 2013.09.13
  • 심사 : 2013.12.02
  • 발행 : 2013.12.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

키워드

참고문헌

  1. M. G. Gericota, G. R. Alves, M. L. Silva, J. M.Ferreira, "A novel methodology for the concurrent test of partial and dynamically reconfigurable SRAM-based FPGAs", IEEE Proceedings of Design, Automation and Test, EuropeConference and Exhibition 2002; 1126, Mar (2002).
  2. S. Molavi, T. McPheeters; "Concurrent Test Implementations", 16th Asian Test Symposium, 2007, 214, Oct (2007).
  3. J. Ma, J. Lee, M. Tehranipoor; "Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths", 27th IEEE VLSI Test Symposium, VTS '09, 221, May (2009).
  4. I. Polian, A. Czutro, S. Kundu, B. Becker; "Power Droop Testing", International Conference on Computer Design 2006, ICCD 2006, 243, Oct (2007).
  5. Pan, Y. C., Mughal, U. A., Rifani, M. C., Wilson, T. M., "Mixed Signal validation of the Intel(R) Pentium (R) 4 microprocessor power-up sequence", Electrical Performance of Electronic Packaging, 2003, 163, Oct (2003).
  6. K. Arabi, "Power noise and its impact on production test and validation of SOC devices", 28th VLSI Test Symposium (VTS), 285, April (2010).
  7. F. N. Tan, S. C. Lee, F. Abdul Rahman, "Finding the worst case supply noiseexcitation methodology for high speed I/O interfaces", 3rd Asia Symposium on Quality Electronic Design, 161, July (2011).