References
- Robert S. P., "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs," Proceedings of the IEEE, vol.94, no.6, pp.1214-1224, June 2006. https://doi.org/10.1109/JPROC.2006.873612
- W. Rhett D., John W., Stephen M., Jian X., Hao H., Christopher M., Ambarish M. S., Michael S., and Paul D. F., "Demystifying 3D ICs: the pros and cons of going vertical," Design & Test of Computers, IEEE , vol.22, no.6, pp. 498 - 510, Nov.-Dec. 2005. https://doi.org/10.1109/MDT.2005.136
- Philip G., Christopher B., and Peter R., "Handbook of 3D Integration: Technology and Application of 3D Integrated Circuits Volume 1 & 2," published by WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim, 2008, ISBN: 978-3-527-32034-9
- Hsien-Hsin S. L., and Krishnendu C., "Test Challenges for 3D Integrated Circuits," Design &Test of Computers, IEEE, vol.26, no.5, pp.26-35, Sept.-Oct. 2009.
- Erik J. M., and Yervant Z., "Testing 3D chips containing through-silicon vias," International Test Conference (ITC) 2009, pp.1-11, Nov. 2009.
- Erik J. M., "Testing TSV based three dimensional stacked ICs," Design, Automation &Test in Europe Conference &Exhibition (DATE) 2010, pp.1689-1694, March 2010.
- Erik J. M., Jouke V., and Mario K., "A structured and scalable test access architecture for TSV-based 3D stacked ICs," VLSI Test Symposium (VTS) 2010, pp.269-274, April 2010.
- 김화영, 오정섭, 박성주, "Redundancy TSV 연결 테스트를 위한 래퍼셀 설계," 대한전자공학회, 전자공학회논문지-SD, 제48권 SD편 제8호, page(s): 18-24, 2011년 8월
- 나현석, 김두환, 조경록, "3-D 구조에서 TSV의 전달 지연 분석," 대한전자공학회, 대한전자공학회 2010년 하계종합학술대회, page(s): 569-572, 2010 년 6월
- Pamela G. and Francis W., "Delay test of chip I/Os using lssd boundary scan," International Test Conference (ITC), pp.83-90, 1998.
- Ken S., Peter H., Mike J., Reed G. and Eric S., "Evaluation of TSV and Micro-Bump Probing for Wide I/O Testing," International Test Conference (ITC) 2011, pp.1-10, 2011.
- Po-Lin C., Jhih-Wei L., and Tsin-Yuan C., "IEEE Standard 1500 Compatible Delay Test Framework," IEEE Transaction on Very Large Scale Integration (VLSI) System, Vol. 17, No. 8, August 2009.
- Qiang X., and Nicola N., "DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs," IEEE Transactions on Computers, Vol. 55, No. 4, April 2006.
- Chih-Yen L., Chen-Hsing W., Kuo-Liang C., Jing-Reng H., Chih-Wea W., Shin-Moe W., and Cheng-Wen W., "STEAC: A Platform for Automatic SOC Test Integration," IEEE Transactions on Very Large Scale Integration (VLSI) System, Vol. 15, No. 4, April 2007.
- "IEEE Standard Testability Method for Embedded Core-based Integrated Circuits," IEEE Std 1500-2005, pp.1-117, 2012.