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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Yield Enhancement Techniques for 3D Memories by Redundancy Sharing among All Layers

  • Lee, Joo-Hwan (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Park, Ki-Hyun (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
  • Received : 2011.10.10
  • Accepted : 2011.12.12
  • Published : 2012.06.01
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Abstract

Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multilayer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

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