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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Secure Hardware Implementation of ARIA Based on Adaptive Random Masking Technique

  • Kang, Jun-Ki (Cyber Security-Convergence Research Department, ETRI, University of Science and Technology) ;
  • Choi, Doo-Ho (Cyber Security-Convergence Research Department, ETRI) ;
  • Choi, Yong-Je (Cyber Security-Convergence Research Department, ETRI) ;
  • Han, Dong-Guk (Department of Mathematics, Kookmin University)
  • Received : 2011.04.25
  • Accepted : 2011.09.06
  • Published : 2012.02.01
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Abstract

The block cipher ARIA has been threatened by side-channel analysis, and much research on countermeasures of this attack has also been produced. However, studies on countermeasures of ARIA are focused on software implementation, and there are no reports about hardware designs and their performance evaluation. Therefore, this article presents an advanced masking algorithm which is strong against second-order differential power analysis (SODPA) and implements a secure ARIA hardware. As there is no comparable report, the proposed masking algorithm used in our hardware module is evaluated using a comparison result of software implementations. Furthermore, we implement the proposed algorithm in three types of hardware architectures and compare them. The smallest module is 10,740 gates in size and consumes an average of 47.47 ${\mu}W$ in power consumption. Finally, we make ASIC chips with the proposed design, and then perform security verification. As a result, the proposed module is small, energy efficient, and secure against SODPA.

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References

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