전기학회논문지 (The Transactions of The Korean Institute of Electrical Engineers)

  • 제61권11호
  • /
  • Pages.1695-1699
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  • 2012
  • /
  • 1975-8359(pISSN)
  • /
  • 2287-4364(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
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광대역 전디지털 클록 데이터 복원회로 설계

Design of Wide-range All Digital Clock and Data Recovery Circuit

  • 투고 : 2012.08.22
  • 심사 : 2012.09.13
  • 발행 : 2012.11.01
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초록

This paper is proposed all digital wide-range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per $2{\pi}$/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13um CMOS process and verified simulation to spectre tool.

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참고문헌

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