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Designing Impedance Network at Quasi Z-Source Inverters by Considering ESR in the Capacitor

커패시터의 ESR을 고려한 Quasi Z-소스 인버터의 임피던스 네트워크 설계

  • Received : 2012.07.18
  • Accepted : 2012.09.13
  • Published : 2012.10.20

Abstract

This paper proposes the method to design the parameters of an impedance network at three-phase QZSI(quasi Z-source inverter) by considering an equivalent series resistance (ESR) in the capacitor. The equations of both two capacitor voltages and two inductor currents are derived at three operating modes of the QZSI. The capacitor voltage ripples caused by the ESR in the capacitor at the transition state of operating modes are calculated. Based on the ripples of both the capacitor voltages and inductor currents, the optimal values of capacitor and inductor are designed. The simulation studies using PSIM and experimental results with DSP are carried out to verify the performance of design method.

Keywords

References

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  3. Enhanced Voltage Gain Single-Phase Current-Fed qZ-Source Inverter vol.18, pp.4, 2013, https://doi.org/10.6113/TKPE.2013.18.4.305