참고문헌
- K. Takeda et al., "A read-staticnoise- margin-free SRAM cell for low-VDD and high-speed applications", IEEE Journal of Solid-State Circuits, vol. 41, pp. 113-121, January 2006. https://doi.org/10.1109/JSSC.2005.859030
- L. Chang et al., "Stable SRAM cell design for the 32 nm node and beyond", in Symposium on VLSI Technology, Japan, pp. 128-129, 2005.
- N. Verma and A. P. Chandrakasan, "A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy", IEEE Journal of Solid-State Circuits, vol. 43, pp. 141-149, January 2008. https://doi.org/10.1109/JSSC.2007.908005
- L. Chang et al., "An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches", IEEE Journal of Solid-State Circuits, vol. 43, pp. 956-963, April 2008. https://doi.org/10.1109/JSSC.2007.917509
- Z. Liu and V. Kursun, "Characterization of a novel nine-transistor SRAM cell", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, pp. 488-492, April 2008. https://doi.org/10.1109/TVLSI.2007.915499
- B. H. Calhoun and A. P. Chandrakasan, "A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation", IEEE Journal of Solid-State Circuits, vol. 42, pp. 680-688, March 2007 https://doi.org/10.1109/JSSC.2006.891726
- T. -H. Kim, J. Liu, J. Keane, and C. H. Kim, "A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing", IEEE Journal of Solid-State Circuits, vol. 43, pp. 518-529, February 2008. https://doi.org/10.1109/JSSC.2007.914328
-
M. -F. Chang et al., "A differential data-aware power-supplied
$(D^{2}AP)$ 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications", IEEE Journal of Solid-State Circuits, vol. 45, pp. 1234-1245, June 2010 https://doi.org/10.1109/JSSC.2010.2048496 - Y. Chung and D. -Y. Lee, "Differential-read symmetrical 8T SRAM bit-cell with enhanced data stability", Electronics Letters, vol. 46, pp. 1258-1260, September 2010. https://doi.org/10.1049/el.2010.1378
- J. P. Kulkarni, K. Kim, and K. Roy, "A 160 mV robust Schmitt trigger based subthreshold SRAM", IEEE Journal of Solid-State Circuits, vol. 42, pp. 2303-2313, October 2007. https://doi.org/10.1109/JSSC.2007.897148
- I. J. Chang et al., "A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS", IEEE Journal of Solid-State Circuits, vol. 44, pp. 650-658, February 2009. https://doi.org/10.1109/JSSC.2008.2011972
-
M. Khare et al., "A high performance 90nm SOI technology with 0.992
${\mu}m^{2}$ 6T-SRAM cell", in International Electron Devices Meeting, USA, pp. 407-410, 2002. - J. Wang, S. Nalam, and B. H. Calhoun, "Analyzing static and dynamic write margin for nanometer SRAMs", in International Symposium on Low Power Electronics and Design, India, pp. 129-134, 2008.
- X. J. Xi et al., "BSIM4.5.0 MOSFET Model - User's Manual", Department of Electrical Engineering and Computer Science, University of California, Berkeley, USA, 2005.
-
Y. Wang et al., "A 1.1 GHz 12
$\mu A$ /Mb-leakage SRAM design in 65 nm ultra-low-power CMOS technology with integrated leakage reduction for mobile applications", IEEE Journal of Solid-State Circuits, vol. 43, pp. 172-179, January 2008. https://doi.org/10.1109/JSSC.2007.907996