JSTS:Journal of Semiconductor Technology and Science

  • 제12권2호
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  • Pages.168-174
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  • 2012
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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High-Speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission

  • Park, Kwang-Il (College of Information & Communication Engineering, Sungkyunkwan University, Memory Division, Samsung Electronics) ;
  • Koo, Ja-Hyuck (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Shin, Won-Hwa (College of Information & Communication Engineering, Sungkyunkwan University, Memory Division, Samsung Electronics) ;
  • Jun, Young-Hyun (Memory Division, Samsung Electronics) ;
  • Kong, Bai-Sun (College of Information & Communication Engineering, Sungkyunkwan University)
  • 투고 : 2011.08.30
  • 발행 : 2012.06.30
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초록

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

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참고문헌

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