전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제49권11호
  • /
  • Pages.141-148
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  • 2012
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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저전력 기법을 사용한 고해상도 오디오용 Sigma Delta Decimation Filter 설계

Sigma Delta Decimation Filter Design for High Resolution Audio Based on Low Power Techniques

  • Au, Huynh Hai (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
  • 투고 : 2012.08.16
  • 발행 : 2012.11.25
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초록

Oversampling 기법을 사용한 analog-to-digital (A/D) 컨버터에서 샘플링 된 신호의 signal bandwidth를 낮추어 주기 위해 데시메이션 필터가 사용된다. 본 논문은 sigma-delta ADC에 사용될 수 있는 저전력 4 단 32 bit 데시메이터 필터 디자인을 제안한다. 디지털 데시메이션 필터는 CIC(cascaded integrator-comb) filter와 세 개의 half-band FIR filter로 이루어져 있다. 전력소모를 최소화하기 위하여 CIC filter에는 pipeline구조가 사용되었고, FIR 필터의 multiplier 구조를 최적화하기 위하여 Canonic Signed Digit (CSD) 코드가 사용되었다. 130nm CMOS 공정으로 설계 자동화 CAD 도구를 사용하여 타이밍, 면적, 전력소모를 최적화하여 98.304 MHz 주파수에서 697 uW의 전력을 소모면서 32 bit, 192 kHz 아웃풋을 낼 수 있다.

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

키워드

참고문헌

  1. Ji Kong et al., "Next-generation consumer audio application specific embedded processor," 2010 IEEE 8th SASP, pp. 1-7, 2010.
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  4. Young-Beom Jang, Se-Jung Yang, Sun-Kook Yoo, "Low-power Decimation Filter Structure for Sigma Delta A/D Converters in Cardiac Applications," The Korean Institute of Electrical Engineers, The Transaction of the Korean Institute of Electrical Engineers, section 53D(2), pp 111-117, Feb 2010.
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  8. Hartley, R, "Optimization of canonic signed digit multipliers for filter design," IEEE International Sympoisum on Circuits and Systems 1991, pp. 1992-1995 vol.4, 11-14 Jun 1991.
  9. Parameswaran S., Krishnapura N., "A 100 $\mu$W Decimator for a 16 bit 24 kHz bandwidth Audio ${\Delta}{\Sigma}$ Modulator," Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2410-2413, May 30 2010-June 2 2010.
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피인용 문헌

  1. 선박엔진성능분석용 웹기반 장기모니터링시스템 구현 vol.39, pp.4, 2015, https://doi.org/10.5916/jkosme.2015.39.4.483