The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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Design of Wide - range Clock and Data Recovery Circuit based Dual-loop DLL using 2-step DPC

2-step DPC를 이용한 이중루프 DLL기반의 광대역 클록 데이터 복원회로 설계

  • 정기상 (전북대학교 전자정보공학부) ;
  • 김강직 (전북대학교 전자정보공학부) ;
  • 고귀한 (전북대학교 전자정보공학부) ;
  • 조성익 (전북대학교 전자정보 공학부)
  • Received : 2011.11.24
  • Accepted : 2012.01.17
  • Published : 2012.02.01
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Abstract

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

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References

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