전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제49권9호
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  • Pages.244-250
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  • 2012
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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접지기반 차동신호 전송을 위한 저전력 4-Gb/s 수신단 설계

Low Power 4-Gb/s Receiver for GND-referenced Differential Signaling

  • 이미라 (성균관대학교 정보통신대학) ;
  • 김석 (성균관대학교 정보통신대학) ;
  • 정영균 (성균관대학교 정보통신대학) ;
  • 배준한 (성균관대학교 정보통신대학) ;
  • 권기원 (성균관대학교 정보통신대학) ;
  • 전정훈 (성균관대학교 정보통신대학)
  • Lee, Mira (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Seok (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Jeong, Youngkyun (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Bae, Jun-Han (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kwon, Kee-Won (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Chun, Jung-Hoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • 투고 : 2012.05.29
  • 발행 : 2012.09.25
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초록

본 논문에서는 접지기반의 저전압 차동 입력 신호를 전달 받는 수신단에 대해 기술하였다. 공통게이트단으로 구성된 레벨시프터와 실시간 선형 이퀄라이저를 이용하여, 채널을 통과하며 왜곡된 신호의 전압 마진과 시간 마진을 확보하였다. 입력 신호의 공통모드 전압이 변하더라도, 레벨시프터에 공급되는 전류의 양을 일정하게 유지 할 수 있는 바이어스 회로를 추가하였다. 저전력 65-nm CMOS 공정으로 수신단회로를 구현하고 측정하였다. -19.7dB의 감쇄를 보이는 FR4 PCB 채널을 통해 4-Gb/s 400mVp-p 차동 신호를 수신단으로 전달하였을 때 $10^{-11}$ BER기준 0.48UI의 시간 마진을 얻을 수 있었으며, 0.30mW/Gb/s의 낮은 전력 소모를 유지하였다.

This paper describes a 4-Gb/s receiver circuit for a low-swing ground-referenced differential signaling system. The receiver employs a common-gate level-shifter and a continuous linear equalizer which compensates inter-symbol-interference (ISI) and improves voltage and timing margins. A bias circuit maintains the bias current of the level-shifter when the common level of the input signal changes. The receiver is implemented with a low-power 65-nm CMOS technology. When 4-Gb/s 400mVp-p signals are transmitted to the receiver through the channel with the attenuation of -19.7dB, the timing margin based on bit error rate (BER) of $10^{-11}$ is 0.48UI and the power consumption is as low as 0.30mW/Gb/s.

키워드

참고문헌

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피인용 문헌

  1. A Receiver for Dual-Channel CIS Interfaces vol.51, pp.10, 2014, https://doi.org/10.5573/ieie.2014.51.10.087